added XML parsing for circuit model ports
This commit is contained in:
tangxifan
parent
c20e1d48d2
commit
999c364b25
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@ -16,6 +16,9 @@
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#include "arch_error.h"
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#include "read_xml_util.h"
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/* Headers from openfpga_utils*/
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#include "string_token.h"
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#include "read_xml_circuit_library.h"
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/********************************************************************
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@ -163,6 +166,50 @@ e_circuit_model_gate_type string_to_gate_type(const std::string& type_string) {
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return NUM_CIRCUIT_MODEL_GATE_TYPES;
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}
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/********************************************************************
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* Convert string to the enumerate of circuit model port type
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*******************************************************************/
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static
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e_circuit_model_port_type string_to_circuit_model_port_type(const std::string& type_string) {
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if (std::string("input") == type_string) {
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return CIRCUIT_MODEL_PORT_INPUT;
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}
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if (std::string("output") == type_string) {
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return CIRCUIT_MODEL_PORT_OUTPUT;
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}
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if (std::string("clock") == type_string) {
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return CIRCUIT_MODEL_PORT_CLOCK;
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}
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if (std::string("sram") == type_string) {
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return CIRCUIT_MODEL_PORT_SRAM;
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}
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if (std::string("bl") == type_string) {
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return CIRCUIT_MODEL_PORT_BL;
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}
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if (std::string("wl") == type_string) {
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return CIRCUIT_MODEL_PORT_WL;
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}
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if (std::string("blb") == type_string) {
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return CIRCUIT_MODEL_PORT_BLB;
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}
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if (std::string("wlb") == type_string) {
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return CIRCUIT_MODEL_PORT_WLB;
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}
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if (std::string("inout") == type_string) {
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return CIRCUIT_MODEL_PORT_INOUT;
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}
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return NUM_CIRCUIT_MODEL_PORT_TYPES;
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}
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/********************************************************************
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* Parse XML codes of design technology of a circuit model to circuit library
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*******************************************************************/
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@ -331,6 +378,141 @@ std::string read_xml_buffer(pugi::xml_node& xml_buffer,
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return buffer_circuit_model_name;
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}
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/********************************************************************
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* Identify the output mask of the port in LUTs,
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* by default it will be applied to each pin of this port
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* This is only applicable to output ports of a LUT
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*******************************************************************/
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static
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void read_xml_output_mask(pugi::xml_node& xml_port,
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const pugiutil::loc_data& loc_data,
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CircuitLibrary& circuit_lib, const CircuitPortId& port) {
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const char* output_mask_attr = get_attribute(xml_port, "lut_output_mask", loc_data, pugiutil::ReqOpt::OPTIONAL).value();
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std::vector<size_t> mask_vector;
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if (nullptr != output_mask_attr) {
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/* Split the string with token ',' */
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StringToken string_tokenizer(get_attribute(xml_port, "lut_output_mask", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(nullptr));
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for (const std::string& mask_token : string_tokenizer.split(',')) {
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mask_vector.push_back(std::atoi(mask_token.c_str()));
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}
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/* Make sure that the size of mask fits the port size */
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if (circuit_lib.port_size(port) != mask_vector.size()) {
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archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_port),
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"Invalid lut_output_mask attribute '%s'! It must match the port size (=%lu)\n",
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output_mask_attr, circuit_lib.port_size(port));
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}
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} else {
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/* By default, we give a mask vector covering each pin of the port */
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mask_vector.resize(circuit_lib.port_size(port));
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std::iota(mask_vector.begin(), mask_vector.end(), 0);
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}
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circuit_lib.set_port_lut_output_mask(port, mask_vector);
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}
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/********************************************************************
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* This is a generic function to parse XML codes that describe
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* a port of a circuit model to circuit library
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*******************************************************************/
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static
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void read_xml_circuit_port(pugi::xml_node& xml_port,
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const pugiutil::loc_data& loc_data,
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CircuitLibrary& circuit_lib, const CircuitModelId& model) {
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/* Find the type of the circuit port
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* so that we can add a new circuit port to circuit library
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*/
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const char* type_attr = get_attribute(xml_port, "type", loc_data).value();
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/* Translate the type of circuit model to enumerate */
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e_circuit_model_port_type port_type = string_to_circuit_model_port_type(std::string(type_attr));
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if (NUM_CIRCUIT_MODEL_PORT_TYPES == port_type) {
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archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_port),
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"Invalid 'type' attribute '%s'\n",
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type_attr);
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}
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CircuitPortId port = circuit_lib.add_model_port(model, port_type);
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/* Parse the name of the port */
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circuit_lib.set_port_prefix(port, get_attribute(xml_port, "prefix", loc_data).as_string());
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/* Parse the name of the port in cell library. By default, the lib_name is the same as port name */
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const char* lib_name_attr = get_attribute(xml_port, "lib_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(nullptr);
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if (nullptr != lib_name_attr) {
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circuit_lib.set_port_lib_name(port, get_attribute(xml_port, "lib_name", loc_data).as_string());
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} else {
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circuit_lib.set_port_lib_name(port, circuit_lib.port_prefix(port));
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}
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/* Parse the port size, by default it will be 1 */
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circuit_lib.set_port_size(port, get_attribute(xml_port, "size", loc_data).as_int(1));
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/* Identify if the port is for mode selection, this is only applicable to SRAM ports.
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* By default, it will NOT be a mode selection port
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*/
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if (CIRCUIT_MODEL_PORT_SRAM == circuit_lib.port_type(port)) {
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circuit_lib.set_port_is_mode_select(port, get_attribute(xml_port, "mode_select", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
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}
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/* Identify the default value of the port, by default it will be 0 */
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circuit_lib.set_port_default_value(port, get_attribute(xml_port, "default_val", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0));
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/* Identify the tri-state map of the port, by default it will be nullptr
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* This is only applicable to input ports of a LUT
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*/
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if ( (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model))
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&& (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port)) ) {
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const char* tri_state_map_attr = get_attribute(xml_port, "tri_state_map", loc_data, pugiutil::ReqOpt::OPTIONAL).value();
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if (nullptr != tri_state_map_attr) {
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circuit_lib.set_port_tri_state_map(port, get_attribute(xml_port, "tri_state_map", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string());
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}
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}
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/* Identify the fracturable-level of the port in LUTs, by default it will be -1
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* This is only applicable to output ports of a LUT
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*/
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if ( (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model))
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&& (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port)) ) {
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circuit_lib.set_port_lut_frac_level(port, get_attribute(xml_port, "lut_frac_level", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1));
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}
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/* Identify the output mask of the port in LUTs, by default it will be applied to each pin of this port
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* This is only applicable to output ports of a LUT
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*/
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if ( (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model))
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&& (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port)) ) {
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read_xml_output_mask(xml_port, loc_data, circuit_lib, port);
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}
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/* Identify if the port is a global port, by default it is NOT */
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circuit_lib.set_port_is_global(port, get_attribute(xml_port, "is_global", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
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/* Identify if the port is a reset port, by default it is NOT */
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circuit_lib.set_port_is_reset(port, get_attribute(xml_port, "is_reset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
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/* Identify if the port is a set port, by default it is NOT */
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circuit_lib.set_port_is_set(port, get_attribute(xml_port, "is_set", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
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/* Identify if the port is in programming purpose, by default it is NOT */
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circuit_lib.set_port_is_prog(port, get_attribute(xml_port, "is_prog", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
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/* Identify if the port is to enable programming for FPGAs, by default it is NOT */
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circuit_lib.set_port_is_config_enable(port, get_attribute(xml_port, "is_config_enable", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
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/* Find the name of circuit model that this port is linked to */
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circuit_lib.set_port_tri_state_model_name(port, get_attribute(xml_port, "circuit_model_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string());
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/* Find the name of circuit model that port is used for inversion of signals,
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* This is only applicable to BL/WL/BLB/WLB ports
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*/
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if ( (CIRCUIT_MODEL_PORT_BL == circuit_lib.port_type(port))
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|| (CIRCUIT_MODEL_PORT_WL == circuit_lib.port_type(port))
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|| (CIRCUIT_MODEL_PORT_BLB == circuit_lib.port_type(port))
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|| (CIRCUIT_MODEL_PORT_WLB == circuit_lib.port_type(port)) ) {
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circuit_lib.set_port_inv_model_name(port, get_attribute(xml_port, "inv_circuit_model_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(nullptr));
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}
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}
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/********************************************************************
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* Parse XML codes of a circuit model to circuit library
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*******************************************************************/
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@ -434,6 +616,15 @@ void read_xml_circuit_model(pugi::xml_node& xml_model,
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auto xml_pass_gate_logic = get_single_child(xml_model, "pass_gate_logic", loc_data);
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circuit_lib.set_model_pass_gate_logic(model, get_attribute(xml_pass_gate_logic, "circuit_model_name", loc_data).as_string());
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}
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/* Parse all the ports belonging to this circuit model
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* We count the number of ports in total and then add one by one
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*/
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size_t num_ports = count_children(xml_model, "port", loc_data, pugiutil::ReqOpt::OPTIONAL);
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for (size_t iport = 0; iport < num_ports; ++iport) {
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auto xml_port = get_first_child(xml_model, "port", loc_data);
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read_xml_circuit_port(xml_port, loc_data, circuit_lib, model);
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}
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}
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/********************************************************************
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