From 98d88dc68647c32b1beebb1aebb02c747eba33df Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 24 Sep 2020 14:13:48 -0600
Subject: [PATCH] [Architecture] Bug fix for vanilla memory organization

---
 .../k4_N4_40nm_standalone_openfpga.xml           | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
index 0781e6caa..43dd1e3f1 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
@@ -146,28 +146,28 @@
       <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
+    <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="bl" prefix="bl" size="1"/>
-       <port type="wl" prefix="wl" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="output" prefix="Qb" lib_name="QN" size="1"/>
     </circuit_model>
     <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
       <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="standalone" circuit_model_name="config_latch"/>
+    <organization type="standalone" circuit_model_name="LATCHR"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>