Updating files to use the updated yosys. Also enabling yosys-plugins compilation

CMakeLists.txt

@@ -232,13 +232,27 @@ include(CheckCXXCompilerFlag)
 add_custom_target(
     yosys ALL 
     COMMAND $(MAKE) config-gcc
-    COMMAND $(MAKE) 
+    COMMAND $(MAKE) install PREFIX=${CMAKE_CURRENT_SOURCE_DIR}/yosys/install
     WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys
     COMMENT "Compile Yosys with given Makefile"
 )
 
 # yosys compilation ends
 
+# yosys-plugins compilation starts
+# run makefile provided, we pass-on the options to the local make file 
+add_custom_target(
+    yosys-plugins ALL 
+    COMMAND $(MAKE) 
+    COMMAND $(MAKE) install 
+    WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys-plugins
+    COMMENT "Compile Yosys-plugins with given Makefile"
+)
+
+add_dependencies(yosys-plugins yosys)
+
+# yosys-plugins compilation ends
+
 # run make to extract compiler options, linker options and list of source files
 #add_custom_target(
 #  yosys

openfpga.sh

@@ -16,6 +16,10 @@ export OPENFPGA_SCRIPT_PATH="${OPENFPGA_PATH}/openfpga_flow/scripts"
 export OPENFPGA_TASK_PATH="${OPENFPGA_PATH}/openfpga_flow/tasks"
 if [ -z $PYTHON_EXEC ]; then export PYTHON_EXEC="python3"; fi
 
+# Add yosys bin folder in PATH, this is required by yosys-plugins 
+# to install plugins in yosys folder
+export PATH="${OPENFPGA_PATH}/yosys/install/bin:${PATH}"
+
 # This function checks the path and
 # raises warning if the command is not executing
 # inside current OpendFPGA folder

openfpga_flow/misc/fpgaflow_default_tool_path.conf

@@ -1,7 +1,7 @@
 # Standard Configuration Example
 [CAD_TOOLS_PATH]
 openfpga_shell_path = ${PATH:OPENFPGA_PATH}/openfpga/openfpga
-yosys_path = ${PATH:OPENFPGA_PATH}/yosys/yosys
+yosys_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys
 misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc
 odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe
 abc_path = ${PATH:OPENFPGA_PATH}/yosys/yosys-abc

openfpga_flow/misc/qlf_yosys.ys

@@ -1,4 +1,7 @@
 # Yosys synthesis script for ${TOP_MODULE}
+
+plugin -i ql-qlf-k4n8
+
 # Read verilog files
 ${READ_VERILOG_FILE}
 

openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys

@@ -65,7 +65,7 @@ opt_expr -mux_undef
 simplemap
 opt_expr
 opt_merge
-opt_rmdff
+#opt_rmdff
 opt_clean
 opt