[core] unique tile identifier done

This commit is contained in:
tangxifan 2023-07-15 22:54:33 -07:00
parent ea8d128789
commit 98c598cec2
5 changed files with 136 additions and 32 deletions

View File

@ -145,34 +145,14 @@ const RRGSB& DeviceRRGSB::get_cb_unique_module(const t_rr_type& cb_type,
/* Give a coordinate of a rr switch block, and return its unique mirror */
const RRGSB& DeviceRRGSB::get_cb_unique_module(
const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate) const {
VTR_ASSERT(validate_cb_type(cb_type));
VTR_ASSERT(validate_coordinate(coordinate));
size_t cb_unique_module_id;
switch (cb_type) {
case CHANX:
cb_unique_module_id =
cbx_unique_module_id_[coordinate.x()][coordinate.y()];
break;
case CHANY:
cb_unique_module_id =
cby_unique_module_id_[coordinate.x()][coordinate.y()];
break;
default:
VTR_LOG_ERROR("Invalid type of connection block!\n");
exit(1);
}
return get_cb_unique_module(cb_type, cb_unique_module_id);
return get_cb_unique_module(cb_type,
get_cb_unique_module_index(cb_type, coordinate));
}
/* Give a coordinate of a rr switch block, and return its unique mirror */
const RRGSB& DeviceRRGSB::get_sb_unique_module(
const vtr::Point<size_t>& coordinate) const {
VTR_ASSERT(validate_coordinate(coordinate));
size_t sb_unique_module_id =
sb_unique_module_id_[coordinate.x()][coordinate.y()];
return get_sb_unique_module(sb_unique_module_id);
return get_sb_unique_module(get_sb_unique_module_index(coordinate));
}
/************************************************************************
@ -550,4 +530,35 @@ bool DeviceRRGSB::validate_cb_type(const t_rr_type& cb_type) const {
return ((CHANX == cb_type) || (CHANY == cb_type));
}
size_t DeviceRRGSB::get_sb_unique_module_index(
const vtr::Point<size_t>& coordinate) const {
VTR_ASSERT(validate_coordinate(coordinate));
size_t sb_unique_module_id =
sb_unique_module_id_[coordinate.x()][coordinate.y()];
return sb_unique_module_id;
}
size_t DeviceRRGSB::get_cb_unique_module_index(
const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate) const {
VTR_ASSERT(validate_cb_type(cb_type));
VTR_ASSERT(validate_coordinate(coordinate));
size_t cb_unique_module_id;
switch (cb_type) {
case CHANX:
cb_unique_module_id =
cbx_unique_module_id_[coordinate.x()][coordinate.y()];
break;
case CHANY:
cb_unique_module_id =
cby_unique_module_id_[coordinate.x()][coordinate.y()];
break;
default:
VTR_LOG_ERROR("Invalid type of connection block!\n");
exit(1);
}
return cb_unique_module_id;
}
} /* End namespace openfpga*/

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@ -59,6 +59,13 @@ class DeviceRRGSB {
size_t get_num_cb_unique_module(const t_rr_type& cb_type)
const; /* get the number of unique mirrors of CBs */
bool is_gsb_exist(const vtr::Point<size_t> coord) const;
/* Get the index of the unique Switch block module with a given GSB
* coordinate. Note: Do NOT use sb coordinate!!! */
size_t get_sb_unique_module_index(const vtr::Point<size_t>& coordinate) const;
/* Get the index of the unique Connection block module with a given GSB
* coordinate. Note: Do NOT use sb coordinate!!! */
size_t get_cb_unique_module_index(const t_rr_type& cb_type,
const vtr::Point<size_t>& coordinate) const;
public: /* Mutators */
void reserve(

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@ -19,9 +19,9 @@ vtr::Point<size_t> FabricTile::tile_coordinate(
FabricTileId FabricTile::unique_tile(const vtr::Point<size_t>& coord) const {
/* Return invalid Id when out of range! */
if (coord.x() < unique_tile_ids_.size()) {
if (coord.y() < unique_tile_ids_[coord.x()].size()) {
return unique_tile_ids_[coord.x()][coord.y()];
if (coord.x() < tile_coord2unique_tile_ids_.size()) {
if (coord.y() < tile_coord2unique_tile_ids_[coord.x()].size()) {
return tile_coord2unique_tile_ids_[coord.x()][coord.y()];
}
}
return FabricTileId::INVALID();
@ -66,9 +66,10 @@ void FabricTile::init(const vtr::Point<size_t>& max_coord) {
for (size_t ix = 0; ix < max_coord.x(); ++ix) {
tile_coord2id_lookup_[ix].resize(max_coord.y(), FabricTileId::INVALID());
}
unique_tile_ids_.resize(max_coord.x());
tile_coord2unique_tile_ids_.resize(max_coord.x());
for (size_t ix = 0; ix < max_coord.x(); ++ix) {
unique_tile_ids_[ix].resize(max_coord.y(), FabricTileId::INVALID());
tile_coord2unique_tile_ids_[ix].resize(max_coord.y(),
FabricTileId::INVALID());
}
}
@ -145,6 +146,7 @@ void FabricTile::clear() {
cby_coords_.clear();
sb_coords_.clear();
tile_coord2id_lookup_.clear();
tile_coord2unique_tile_ids_.clear();
unique_tile_ids_.clear();
}
@ -152,4 +154,68 @@ bool FabricTile::valid_tile_id(const FabricTileId& tile_id) const {
return (size_t(tile_id) < ids_.size()) && (tile_id == ids_[tile_id]);
}
bool FabricTile::equivalent_tile(const FabricTileId& tile_a,
const FabricTileId& tile_b,
const DeviceGrid& grids,
const DeviceRRGSB& device_rr_gsb) const {
/* The pb of two tiles should be the same, otherwise not equivalent */
if (grids.get_physical_type(pb_coords_[tile_a].x(), pb_coords_[tile_a].y()) !=
grids.get_physical_type(pb_coords_[tile_b].x(), pb_coords_[tile_b].y())) {
return false;
}
/* The number of cbx, cby and sb blocks should be the same */
if (cbx_coords_[tile_a].size() != cbx_coords_[tile_b].size() ||
cby_coords_[tile_a].size() != cby_coords_[tile_b].size() ||
sb_coords_[tile_a].size() != sb_coords_[tile_b].size()) {
return false;
}
/* Each CBx should have the same unique modules in the device rr_gsb */
for (size_t iblk = 0; iblk < cbx_coords_[tile_a].size(); ++iblk) {
if (device_rr_gsb.get_cb_unique_module_index(CHANX,
cbx_coords_[tile_a][iblk]) !=
device_rr_gsb.get_cb_unique_module_index(CHANX,
cbx_coords_[tile_b][iblk])) {
return false;
}
}
for (size_t iblk = 0; iblk < cby_coords_[tile_a].size(); ++iblk) {
if (device_rr_gsb.get_cb_unique_module_index(CHANY,
cby_coords_[tile_a][iblk]) !=
device_rr_gsb.get_cb_unique_module_index(CHANY,
cby_coords_[tile_b][iblk])) {
return false;
}
}
for (size_t iblk = 0; iblk < sb_coords_[tile_a].size(); ++iblk) {
if (device_rr_gsb.get_sb_unique_module_index(sb_coords_[tile_a][iblk]) !=
device_rr_gsb.get_sb_unique_module_index(sb_coords_[tile_b][iblk])) {
return false;
}
}
return true;
}
int FabricTile::build_unique_tiles(const DeviceGrid& grids,
const DeviceRRGSB& device_rr_gsb) {
for (size_t ix = 0; ix < grids.width(); ++ix) {
for (size_t iy = 0; iy < grids.height(); ++iy) {
bool is_unique_tile = true;
for (FabricTileId unique_tile_id : unique_tile_ids_) {
if (equivalent_tile(tile_coord2id_lookup_[ix][iy], unique_tile_id,
grids, device_rr_gsb)) {
is_unique_tile = false;
tile_coord2unique_tile_ids_[ix][iy] = unique_tile_id;
break;
}
}
/* Update list if this is a unique tile */
if (is_unique_tile) {
unique_tile_ids_.push_back(tile_coord2unique_tile_ids_[ix][iy]);
tile_coord2unique_tile_ids_[ix][iy] = tile_coord2id_lookup_[ix][iy];
}
}
}
return 0;
}
} /* End namespace openfpga*/

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@ -6,6 +6,7 @@
*******************************************************************/
#include <vector>
#include "device_grid.h"
#include "device_rr_gsb.h"
#include "fabric_tile_fwd.h"
#include "vtr_geometry.h"
@ -52,10 +53,20 @@ class FabricTile {
void clear();
/** @brief Initialize the data with a given range. Used by constructors */
void init(const vtr::Point<size_t>& max_coord);
/** @brief Identify the number of unique tiles and keep in the lookup */
int build_unique_tiles(const DeviceGrid& grids,
const DeviceRRGSB& device_rr_gsb);
public: /* Validators */
bool valid_tile_id(const FabricTileId& tile_id) const;
private: /* Internal validators */
/** @brief Identify if two tile are equivalent in their sub-modules, including
* pb, cbx, cby and sb */
bool equivalent_tile(const FabricTileId& tile_a, const FabricTileId& tile_b,
const DeviceGrid& grids,
const DeviceRRGSB& device_rr_gsb) const;
private: /* Internal builders */
void invalidate_tile_in_lookup(const vtr::Point<size_t>& coord);
bool register_tile_in_lookup(const FabricTileId& tile_id,
@ -72,8 +83,9 @@ class FabricTile {
/* A fast lookup to spot tile by coordinate */
std::vector<std::vector<FabricTileId>> tile_coord2id_lookup_;
std::vector<std::vector<FabricTileId>>
unique_tile_ids_; /* Use [x][y] to get the id of the unique tile with a
given coordinate */
tile_coord2unique_tile_ids_; /* Use [x][y] to get the id of the unique tile
with a given coordinate */
std::vector<FabricTileId> unique_tile_ids_;
};
} /* End namespace openfpga*/

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@ -95,11 +95,11 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile,
const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord);
if (curr_rr_gsb.is_cb_exist(CHANX)) {
fabric_tile.add_cbx_coordinate(curr_tile_id,
curr_rr_gsb.get_cb_coordinate(CHANX));
curr_rr_gsb.get_sb_coordinate());
}
if (curr_rr_gsb.is_cb_exist(CHANY)) {
fabric_tile.add_cby_coordinate(curr_tile_id,
curr_rr_gsb.get_cb_coordinate(CHANY));
curr_rr_gsb.get_sb_coordinate());
}
if (curr_rr_gsb.is_sb_exist()) {
fabric_tile.add_sb_coordinate(curr_tile_id,
@ -133,6 +133,14 @@ int build_fabric_tile(FabricTile& fabric_tile, const TileConfig& tile_config,
status_code = CMD_EXEC_FATAL_ERROR;
}
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
/* Build unique tiles to compress the number of tile modules to be built in
* later steps */
status_code = fabric_tile.build_unique_tiles(grids, device_rr_gsb);
return status_code;
}