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bug fixed in routing_test.v. Deployed to regression tests

This commit is contained in:
tangxifan 2020-05-01 14:47:08 -06:00
parent 6dd8d347e1
commit 98a658a013
2 changed files with 11 additions and 5 deletions
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2
openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v
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@ -1,5 +1,5 @@
module routing_test(IN0,IN1,IN2,OUT0,OUT1,OUT2,clk);
module routing_test(IN0,IN1,IN2, clk, OUT0,OUT1,OUT2);
input wire IN0,IN1,IN2,clk;

14
openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
View File

@ -21,18 +21,24 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
[BENCHMARKS]
#
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif
# Modelsim is ok with this but icarus fails due to poor support on timing and looping
#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif
#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif
[SYNTHESIS_PARAM]
bench0_top = and2
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
bench1_top = and2_latch
bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act
bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
bench1_top = routing_test
bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act
bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v
bench2_top = and2_latch
bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act
bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=