riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

modify document format

This commit is contained in:
Victor 2024-09-11 14:52:32 +08:00
parent 6bb54a406d
commit 989dda9028
1 changed files with 39 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

79
docs/source/manual/file_formats/reference_file.rst
View File

@ -20,58 +20,57 @@ Date: Mon Sep 9 16:41:53 2024
references: references:
- module: grid_io_top - module: grid_io_top
count: 1 count: 1
instances: instances:
- grid_io_top_1__2_ - grid_io_top_1__2_
- module: grid_io_right - module: grid_io_right
count: 1 count: 1
instances: instances:
- grid_io_right_2__1_ - grid_io_right_2__1_
- module: grid_io_bottom - module: grid_io_bottom
count: 1 count: 1
instances: instances:
- grid_io_bottom_1__0_ - grid_io_bottom_1__0_
- module: grid_io_left - module: grid_io_left
count: 1 count: 1
instances: instances:
- grid_io_left_0__1_ - grid_io_left_0__1_
- module: grid_clb - module: grid_clb
count: 1 count: 1
instances: instances:
- grid_clb_1__1_ - grid_clb_1__1_
- module: sb_0__0_ - module: sb_0__0_
count: 1 count: 1
instances: instances:
- sb_0__0_ - sb_0__0_
- module: sb_0__1_ - module: sb_0__1_
count: 1 count: 1
instances: instances:
- sb_0__1_ - sb_0__1_
- module: sb_1__0_ - module: sb_1__0_
count: 1 count: 1
instances: instances:
- sb_1__0_ - sb_1__0_
- module: sb_1__1_ - module: sb_1__1_
count: 1 count: 1
instances: instances:
- sb_1__1_ - sb_1__1_
- module: cbx_1__0_ - module: cbx_1__0_
count: 1 count: 1
instances: instances:
- cbx_1__0_ - cbx_1__0_
- module: cbx_1__1_ - module: cbx_1__1_
count: 1 count: 1
instances: instances:
- cbx_1__1_ - cbx_1__1_
- module: cby_0__1_ - module: cby_0__1_
count: 1 count: 1
instances: instances:
- cby_0__1_ - cby_0__1_
- module: cby_1__1_ - module: cby_1__1_
count: 1 count: 1
instances: instances:
- cby_1__1_ - cby_1__1_
direct_interc
In this example, the parent module is ``fpga_top``. In this example, the parent module is ``fpga_top``.
The child modules under ``fpga_top`` are ``grid_io_top``, ``grid_io_right``, and etc. The child modules under ``fpga_top`` are ``grid_io_top``, ``grid_io_right``, and etc.