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[core] debuggign

This commit is contained in:
tangxifan 2023-03-06 15:57:37 -08:00
parent 1633279c65
commit 9823983b30
2 changed files with 3 additions and 3 deletions
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4
openfpga/src/annotation/append_clock_rr_graph.cpp
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@ -682,8 +682,8 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
vpr_device_ctx.rr_graph_builder.init_fan_in();
VTR_LOGV(verbose, "Apply edge partitioning\n");
vpr_device_ctx.rr_graph_builder.partition_edges();
//VTR_LOGV(verbose, "Building incoming edges\n");
//vpr_device_ctx.rr_graph_builder.build_in_edges();
VTR_LOGV(verbose, "Building incoming edges\n");
vpr_device_ctx.rr_graph_builder.build_in_edges();
/* Report number of added clock nodes and edges */
VTR_LOG(

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit 5795b7df753903b215c1273cfe910113375f6aa8
Subproject commit 69d852d7e968e9033c9f26541fae6e96eca72e5d