From 9823983b300855ea2814b3e03254b9adcde2cdeb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 6 Mar 2023 15:57:37 -0800 Subject: [PATCH] [core] debuggign --- openfpga/src/annotation/append_clock_rr_graph.cpp | 4 ++-- vtr-verilog-to-routing | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 96acadd62..0f848ff36 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -682,8 +682,8 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, vpr_device_ctx.rr_graph_builder.init_fan_in(); VTR_LOGV(verbose, "Apply edge partitioning\n"); vpr_device_ctx.rr_graph_builder.partition_edges(); - //VTR_LOGV(verbose, "Building incoming edges\n"); - //vpr_device_ctx.rr_graph_builder.build_in_edges(); + VTR_LOGV(verbose, "Building incoming edges\n"); + vpr_device_ctx.rr_graph_builder.build_in_edges(); /* Report number of added clock nodes and edges */ VTR_LOG( diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 5795b7df7..69d852d7e 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 5795b7df753903b215c1273cfe910113375f6aa8 +Subproject commit 69d852d7e968e9033c9f26541fae6e96eca72e5d