[arch] upgrade arch file which was designed for v1.1

openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_40nm.xml

@@ -1,4 +1,4 @@
-<!-- 
+<?xml version="1.0" ?><!-- 
   Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
 
   - 40 nm technology
@@ -8,8 +8,7 @@
   - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
 
   Authors: Xifan Tang
--->
+--><architecture> 
-<architecture>
    <!-- 
        ODIN II specific config begins 
        Describes the types of user-specified netlist blocks (in blif, this corresponds to 
@@ -77,7 +76,7 @@
          If you need to register the I/O, define clocks in the circuit models
          These clocks can be handled in back-end
      -->  
-    <tile name="io" capacity="8" area="0">
+      <tile name="io" area="0">   <sub_tile name="io" capacity="8">    
           <equivalent_sites>     
              <site pb_type="io"/>     
           </equivalent_sites>    
@@ -90,8 +89,8 @@
              <loc side="right">io.outpad io.inpad</loc>     
              <loc side="bottom">io.outpad io.inpad</loc>     
           </pinlocations>    
-    </tile>
+       </sub_tile>  </tile>  
-    <tile name="clb" area="53894">
+      <tile name="clb" area="53894">   <sub_tile name="clb">    
           <equivalent_sites>     
              <site pb_type="clb"/>     
           </equivalent_sites>    
@@ -104,7 +103,7 @@
              <fc_override port_name="reset" fc_type="frac" fc_val="0"/>     
           </fc>    
           <pinlocations pattern="spread"/>    
-    </tile>
+       </sub_tile>  </tile>  
    </tiles> 
    <!-- ODIN II specific config ends --> 
    <!-- Physical descriptions begin -->