[Doc] Format openfpga command documentation by using option views

docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst

@@ -14,46 +14,61 @@ Repack's functionality are in the following aspects:
 
 - It re-routes all the nets by considering the programmable interconnects in physical modes **only**.
 
-.. note:: This must be done before bitstream generator and testbench generation. Strongly recommend it is done after all the fix-up have been applied
+  .. note:: This must be done before bitstream generator and testbench generation. Strongly recommend it is done after all the fix-up have been applied
 
-.. option:: --design_constraints 
+  .. option:: --design_constraints 
-
+  
-  Apply design constraints from an external file. 
+    Apply design constraints from an external file. 
-  Normally, repack takes the net mapping from VPR packing and routing results. 
+    Normally, repack takes the net mapping from VPR packing and routing results. 
-  Alternatively, repack can accept the design constraints, in particular, net remapping, from an XML-based design constraint description.
+    Alternatively, repack can accept the design constraints, in particular, net remapping, from an XML-based design constraint description.
-  See details in :ref:`file_formats_repack_design_constraints`.
+    See details in :ref:`file_formats_repack_design_constraints`.
-
+  
-.. warning:: Design constraints are designed to help repacker to identify which clock net to be mapped to which pin, so that multi-clock benchmarks can be correctly implemented, in the case that VPR may not have sufficient vision on clock net mapping. **Try not to use design constraints to remap any other types of nets!!!**
+  .. warning:: Design constraints are designed to help repacker to identify which clock net to be mapped to which pin, so that multi-clock benchmarks can be correctly implemented, in the case that VPR may not have sufficient vision on clock net mapping. **Try not to use design constraints to remap any other types of nets!!!**
-   
+     
-.. option:: --verbose 
+  .. option:: --verbose 
-
+  
-  Show verbose log
+    Show verbose log
 
 build_architecture_bitstream
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
   Decode VPR implementing results to an fabric-independent bitstream database 
   
-  - ``--read_file`` Read the fabric-independent bitstream from an XML file. When this is enabled, bitstream generation will NOT consider VPR results.
+  .. option:: --read_file <string>
 
-  - ``--write_file`` Output the fabric-independent bitstream to an XML file
+    Read the fabric-independent bitstream from an XML file. When this is enabled, bitstream generation will NOT consider VPR results. See details at :ref:`file_formats_architecture_bitstream`.
+
+  .. option:: --write_file <string>
+
+    Output the fabric-independent bitstream to an XML file. See details at :ref:`file_formats_architecture_bitstream`.
   
-  - ``--verbose`` Show verbose log
+  .. option:: --verbose
+
+    Show verbose log
 
 build_fabric_bitstream
 ~~~~~~~~~~~~~~~~~~~~~~
 
   Build a sequence for every configuration bits in the bitstream database for a specific FPGA fabric
 
-  - ``--verbose`` Show verbose log
+  .. option:: --verbose
+
+    Show verbose log
 
 write_fabric_bitstream
 ~~~~~~~~~~~~~~~~~~~~~~
 
   Output the fabric bitstream database to a specific file format
 
-  - ``--file`` or ``-f`` Output the fabric bitstream to an plain text file (only 0 or 1)
+  .. option:: --file <string> or -f <string>
 
-  - ``--format`` Specify the file format [``plain_text`` | ``xml``]. By default is ``plain_text``.
+    Output the fabric bitstream to an plain text file (only ``0`` or ``1``)
 
-  - ``--verbose`` Show verbose log
+  .. option:: --format <string>
+
+    Specify the file format [``plain_text`` | ``xml``]. By default is ``plain_text``.
+    See file formats in :ref:`file_formats_fabric_bitstream_xml` and :ref:`file_formats_fabric_bitstream_plain_text`.
+
+  .. option:: --verbose
+
+    Show verbose log

docs/source/manual/openfpga_shell/openfpga_commands/fpga_sdc_commands.rst

@@ -8,77 +8,127 @@ write_pnr_sdc
  
   Write the SDC files for PnR backend
   
-  - ``--file`` or ``-f`` Specify the output directory for SDC files
+  .. option:: --file <string> or -f <string>
-
+  
-  - ``--hierarchical`` Output SDC files without full path in hierarchy
+    Specify the output directory for SDC files
-
+    For example, ``--file /temp/pnr_sdc``
-  - ``--flatten_names`` Use flatten names (no wildcards) in SDC files
+  
-
+  .. option:: --hierarchical 
-  - ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
+  
-
+    Output SDC files without full path in hierarchy
-  - ``--output_hierarchy`` Output hierarchy of Multiple-Instance-Blocks(MIBs) to plain text file. This is applied to constrain timing for grids, Switch Blocks and Connection Blocks. 
+  
-
+  .. option:: --flatten_names
-    .. note:: Valid only when ``compress_routing`` is enabled in ``build_fabric``
+  
-
+     Use flatten names (no wildcards) in SDC files
-  - ``--constrain_global_port`` Constrain all the global ports of FPGA fabric.
+  
-
+  .. option:: --time_unit <string>
-  - ``--constrain_non_clock_global_port`` Constrain all the non-clock global ports as clocks ports of FPGA fabric
+      
-
+    Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
-    .. note:: ``constrain_global_port`` will treat these global ports in Clock Tree Synthesis (CTS), in purpose of balancing the delay to each sink. Be carefull to enable ``constrain_non_clock_global_port``, this may significanly increase the runtime of CTS as it is supposed to be routed before any other nets. This may cause routing congestion as well.
+  
-
+   
-  - ``--constrain_grid`` Constrain all the grids of FPGA fabric
+  .. option:: --output_hierarchy
-
+  
-  - ``--constrain_sb`` Constrain all the switch blocks of FPGA fabric
+    Output hierarchy of Multiple-Instance-Blocks(MIBs) to plain text file. This is applied to constrain timing for grids, Switch Blocks and Connection Blocks. 
-
+  
-  - ``--constrain_cb`` Constrain all the connection blocks of FPGA fabric
+    .. note:: Valid only when ``compress_routing`` is enabled in ``build_fabric``
-
+  
-  - ``--constrain_configurable_memory_outputs`` Constrain all the outputs of configurable memories of FPGA fabric
+  .. option:: --constrain_global_port
-
+  
-  - ``--constrain_routing_multiplexer_outputs`` Constrain all the outputs of routing multiplexer of FPGA fabric
+    Constrain all the global ports of FPGA fabric.
-
+  
-  - ``--constrain_switch_block_outputs`` Constrain all the outputs of switch blocks of FPGA fabric
+  .. option:: --constrain_non_clock_global_port
-
+  
-  - ``--constrain_zero_delay_paths`` Constrain all the zero-delay paths in FPGA fabric
+    Constrain all the non-clock global ports as clocks ports of FPGA fabric
-
+  
-    .. note:: Zero-delay path may cause errors in some PnR tools as it is considered illegal
+    .. note:: ``constrain_global_port`` will treat these global ports in Clock Tree Synthesis (CTS), in purpose of balancing the delay to each sink. Be carefull to enable ``constrain_non_clock_global_port``, this may significanly increase the runtime of CTS as it is supposed to be routed before any other nets. This may cause routing congestion as well.
+  
+  .. option:: --constrain_grid
+  
+    Constrain all the grids of FPGA fabric
+  
+  .. option:: --constrain_sb
+  
+    Constrain all the switch blocks of FPGA fabric
+  
+  .. option:: --constrain_cb
+  
+    Constrain all the connection blocks of FPGA fabric
+  
+  .. option:: --constrain_configurable_memory_outputs
+  
+    Constrain all the outputs of configurable memories of FPGA fabric
+  
+  .. option:: --constrain_routing_multiplexer_outputs
+  
+    Constrain all the outputs of routing multiplexer of FPGA fabric
+  
+  .. option:: --constrain_switch_block_outputs
+  
+    Constrain all the outputs of switch blocks of FPGA fabric
+  
+  .. option:: --constrain_zero_delay_paths
+  
+    Constrain all the zero-delay paths in FPGA fabric
+  
+    .. note:: Zero-delay path may cause errors in some PnR tools as it is considered illegal
+    
+  .. option:: --verbose
+  
+    Enable verbose output
   
-  - ``--verbose`` Enable verbose output
-
 write_configuration_chain_sdc
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  
   Write the SDC file to constrain the timing for configuration chain. The timing constraints will always start from the first output (Q) of a Configuration Chain Flip-flop (CCFF) and ends at the inputs of the next CCFF in the chain. Note that Qb of CCFF will not be constrained!
 
-  - ``--file`` or ``-f`` Specify the output SDC file
+  .. option:: --file <string> or -f <string> 
-
-  - ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
-
   
-  - ``--max_delay`` Specify the maximum delay to be used. The timing value should follow the time unit defined in this command.
+    Specify the output SDC file. For example, ``--file cc_chain.sdc``
-
+  
-  - ``--min_delay`` Specify the minimum delay to be used. The timing value should follow the time unit defined in this command.
+  .. option:: --time_unit <string>
-
+  
-  .. note::
+    Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
-     Only applicable when configuration chain is used as configuration protocol
+  
+  .. option:: --max_delay <float>
+  
+    Specify the maximum delay to be used. The timing value should follow the time unit defined in this command.
+  
+  .. option:: --min_delay <float>
+  
+    Specify the minimum delay to be used. The timing value should follow the time unit defined in this command.
+  
+    .. note:: Only applicable when configuration chain is used as configuration protocol
 
 write_sdc_disable_timing_configure_ports
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
   Write the SDC file to disable timing for configure ports of programmable modules. The SDC aims to break the combinational loops across FPGAs and avoid false path timing to be visible to timing analyzers
 
-  - ``--file`` or ``-f`` Specify the output SDC file
+  .. option:: --file <string> or -f <string> 
-
+  
-  - ``--flatten_names`` Use flatten names (no wildcards) in SDC files
+    Specify the output SDC file. For example, ``--file disable_config_timing.sdc``.
-
+  
-  - ``--verbose`` Show verbose log
+  .. option:: --flatten_names
+  
+    Use flatten names (no wildcards) in SDC files
+  
+  .. option:: --verbose
+  
+    Show verbose log
 
 write_analysis_sdc
 ~~~~~~~~~~~~~~~~~~
 
   Write the SDC to run timing analysis for a mapped FPGA fabric
 
-  - ``--file`` or ``-f`` Specify the output directory for SDC files
+  .. option:: --file <string> or -f <string>
-  
-  - ``--flatten_names`` Use flatten names (no wildcards) in SDC files
 
-  - ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
+    Specify the output directory for SDC files. For example, ``--file counter_sta_analysis.sdc``
+  
+  .. option:: --flatten_names
+
+    Use flatten names (no wildcards) in SDC files
+
+  .. option:: --time_unit <string>
+
+    Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).

docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst

@@ -8,43 +8,78 @@ write_fabric_verilog
 
   Write the Verilog netlist for FPGA fabric based on module graph
 
-  - ``--file`` or ``-f`` Specify the output directory for the Verilog netlists
+  .. option:: --file <string> or -f <string> 
 
-  - ``--explicit_port_mapping`` Use explicit port mapping when writing the Verilog netlists
+    Specify the output directory for the Verilog netlists. For example, ``--file /temp/fabric_netlist/``
 
-  - ``--include_timing`` Output timing information to Verilog netlists for primitive modules
+  .. option:: --explicit_port_mapping
+
+    Use explicit port mapping when writing the Verilog netlists
+
+  .. option:: --include_timing
+
+    Output timing information to Verilog netlists for primitive modules
  
-  - ``--include_signal_init`` Output signal initialization to Verilog netlists for primitive modules
+  .. option:: --include_signal_init
 
-  - ``--support_icarus_simulator`` Output Verilog netlists with syntax that iVerilog simulatorcan accept
+    Output signal initialization to Verilog netlists for primitive modules
 
-  - ``--print_user_defined_template`` Output a template Verilog netlist for all the user-defined ``circuit models`` in :ref:`circuit_library`. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists
+  .. option:: --support_icarus_simulator
+     
+    Output Verilog netlists with syntax that iVerilog simulatorcan accept
 
-  - ``--verbose`` Show verbose log
+  .. option:: --print_user_defined_template
+
+    Output a template Verilog netlist for all the user-defined ``circuit models`` in :ref:`circuit_library`. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists
+
+  .. option:: --verbose
+
+    Show verbose log
 
 write_verilog_testbench
 ~~~~~~~~~~~~~~~~~~~~~~~
  
   Write the Verilog testbench for FPGA fabric
 
-  - ``--file`` or ``-f`` The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists
+  .. option:: --file <string> or -f <string>
+     
+    The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists. For example, ``--file /temp/testbench``
 
-  - ``--fabric_netlist_file_path`` Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names.
+  .. option:: --fabric_netlist_file_path <string>
 
-  - ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches
+    Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names. For example, ``--file /temp/fabric/fabric_netlists.v``
 
-  - ``--pin_constraints_file`` specify the *Pin Constraints File* (PCF) if you want to custom stimulus in  testbenches. Strongly recommend for multi-clock simulations. See detailed file format about :ref:`file_format_pin_constraints_file`.
+  .. option:: --reference_benchmark_file_path <string>
 
-  - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. 
+    Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
+
+  .. option:: --pin_constraints_file <string>
+
+    Specify the *Pin Constraints File* (PCF) if you want to custom stimulus in testbenches. For example, ``pin_constraints_file pin_constraints.xml``
+    Strongly recommend for multi-clock simulations. See detailed file format about :ref:`file_format_pin_constraints_file`.
+
+  .. option:: --fast_configuration
+
+    Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. 
 
     .. note:: If both reset and set ports are defined in the circuit modeling for programming, OpenFPGA will pick the one that will bring largest benefit in speeding up configuration.
 
-  - ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+  .. option:: --print_top_testbench
 
-  - ``--print_formal_verification_top_netlist`` Generate a top-level module which can be used in formal verification
+    Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 
-  - ``--print_preconfig_top_testbench`` Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+  .. option:: --print_formal_verification_top_netlist
 
-  - ``--print_simulation_ini`` Output an exchangeable simulation ini file, which is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+    Generate a top-level module which can be used in formal verification
 
-  - ``--explicit_port_mapping`` Use explicit port mapping when writing the Verilog netlists
+  .. option:: --print_preconfig_top_testbench
+
+    Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+
+  .. option:: --print_simulation_ini <string>
+
+    Output an exchangeable simulation ini file, which is needed only when you need to interface different HDL simulators using openfpga flow-run scripts. For example, ``--print_simulation_ini /temp/testbench/sim.ini``
+
+  .. option:: --explicit_port_mapping
+
+    Use explicit port mapping when writing the Verilog netlists

docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst

@@ -8,56 +8,83 @@ read_openfpga_arch
 
   Read the XML file about architecture description (see details in :ref:`arch_generality`)
 
-  - ``--file`` or ``-f`` Specify the file name 
+  .. option:: --file <string> or -f <string>
+     
+    Specify the file name. For example, ``--file openfpga_arch.xml`` 
 
-  - ``--verbose`` Show verbose log
+  .. option:: --verbose
+
+    Show verbose log
 
 write_openfpga_arch
 ~~~~~~~~~~~~~~~~~~~
 
   Write the OpenFPGA XML architecture file to a file
 
-  - ``--file`` or ``-f`` Specify the file name 
+  .. option:: --file <string> or -f <string>
+     
+    Specify the file name. For example, ``--file arch_echo.xml`` 
 
-  - ``--verbose`` Show verbose log
+  .. option:: --verbose
+
+    Show verbose log
 
 read_openfpga_simulation_setting
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
   Read the XML file about simulation settings (see details in :ref:`simulation_setting`)
 
-  - ``--file`` or ``-f`` Specify the file name 
+  .. option:: --file <string> or -f <string>
+     
+    Specify the file name. For example, ``--file auto_simulation_setting.xml`` 
 
-  - ``--verbose`` Show verbose log
+  .. option:: --verbose
+
+    Show verbose log
 
 write_openfpga_simulation_setting
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
   Write the OpenFPGA XML simulation settings to a file
 
-  - ``--file`` or ``-f`` Specify the file name 
+  .. option:: --file <string> or -f <string>
+     
+    Specify the file name. For example, ``--file auto_simulation_setting_echo.xml`` 
 
-  - ``--verbose`` Show verbose log
+  .. option:: --verbose
+
+    Show verbose log
 
 link_openfpga_arch
 ~~~~~~~~~~~~~~~~~~
 
   Annotate the OpenFPGA architecture to VPR data base
 
-  - ``--activity_file`` Specify the signal activity file
+  .. option:: --activity_file <string>
 
-  - ``--sort_gsb_chan_node_in_edges`` Sort the edges for the routing tracks in General Switch Blocks (GSBs). Strongly recommand to turn this on for uniquifying the routing modules
+    Specify the signal activity file. For example, ``--activity_file counter.act``
 
-  - ``--verbose`` Show verbose log
+  .. option:: --sort_gsb_chan_node_in_edges
+
+    Sort the edges for the routing tracks in General Switch Blocks (GSBs). Strongly recommand to turn this on for uniquifying the routing modules
+
+  .. option:: --verbose
+
+    Show verbose log
 
 write_gsb_to_xml
 ~~~~~~~~~~~~~~~~
 
   Write the internal structure of General Switch Blocks (GSBs) across a FPGA fabric, including the interconnection between the nodes and node-level details, to XML files
 
-  - ``--file`` or ``-f`` Specify the output directory of the XML files. Each GSB will be written to an indepedent XML file
+  .. option:: --file <string> or -f <string>
 
-  - ``--verbose`` Show verbose log
+    Specify the output directory of the XML files. Each GSB will be written to an indepedent XML file
+    For example, ``--file /temp/gsb_output``
+
+  .. option:: --verbose
+
+    Show verbose log
 
   .. note:: This command is used to help users to study the difference between GSBs
 
@@ -69,9 +96,13 @@ check_netlist_naming_conflict
 
   .. warning:: This command may be deprecated in future when it is merged to VPR upstream
   
-  - ``--fix`` Apply fix-up to the names that violate the syntax
+  .. option:: --fix
 
-  - ``--report <.xml>`` Report the naming fix-up to a log file
+    Apply fix-up to the names that violate the syntax
+
+  .. option:: --report <string>
+
+    Report the naming fix-up to an XML-based log file. For example, ``--report rename.xml``
 
 pb_pin_fixup
 ~~~~~~~~~~~~
@@ -81,7 +112,9 @@ pb_pin_fixup
 
   .. warning:: This command may be deprecated in future when it is merged to VPR upstream
   
-  - ``--verbose`` Show verbose log
+  .. option:: --verbose
+
+    Show verbose log
    
 lut_truth_table_fixup
 ~~~~~~~~~~~~~~~~~~~~~
@@ -90,7 +123,9 @@ lut_truth_table_fixup
 
   .. warning:: This command may be deprecated in future when it is merged to VPR upstream
 
-  - ``--verbose`` Show verbose log
+  .. option:: --verbose
+
+    Show verbose log
 
 .. _cmd_build_fabric:
   
@@ -99,21 +134,35 @@ build_fabric
 
   Build the module graph.
 
-  - ``--compress_routing`` Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.
+  .. option:: --compress_routing
+
+    Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.
   
-  - ``--duplicate_grid_pin`` Enable pin duplication on grid modules. This is optional unless ultra-dense layout generation is needed
+  .. option:: --duplicate_grid_pin
 
-  - ``--load_fabric_key <xml_file>`` Load an external fabric key from an XML file.
+    Enable pin duplication on grid modules. This is optional unless ultra-dense layout generation is needed
 
-  - ``--generate_fabric_key`` Generate a fabric key in a random way
+  .. option:: --load_fabric_key <string>
 
-  - ``--write_fabric_key <xml_file>`` Output current fabric key to an XML file
+    Load an external fabric key from an XML file. For example, ``--load_fabric_key fpga_2x2.xml`` See details in :ref:`file_formats_fabric_key`.
 
-  - ``--frame_view`` Create only frame views of the module graph. When enabled, top-level module will not include any nets. This option is made for save runtime and memory.
+  .. option:: --generate_fabric_key
+
+    Generate a fabric key in a random way
+
+  .. option:: --write_fabric_key <string>.
+
+    Output current fabric key to an XML file. For example, ``--load_fabric_key fpga_2x2.xml`` See details in :ref:`file_formats_fabric_key`.
+
+  .. option:: --frame_view
+
+    Create only frame views of the module graph. When enabled, top-level module will not include any nets. This option is made for save runtime and memory.
 
     .. warning:: Recommend to turn the option on when bitstream generation is the only purpose of the flow. Do not use it when you need generate netlists!
 
-  - ``--verbose`` Show verbose log
+  .. option:: --verbose
+
+    Show verbose log
 
   .. note:: This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE
 
@@ -122,10 +171,16 @@ write_fabric_hierarchy
 
   Write the hierarchy of FPGA fabric graph to a plain-text file
   
-  - ``--file`` or ``-f`` Specify the file name to write the hierarchy. 
+  .. option:: --file <string> or -f <string>
+  
+    Specify the file name to write the hierarchy. 
 
-  - ``--depth`` Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1. 
+  .. option:: --depth <int>
 
-  - ``--verbose`` Show verbose log
+    Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1. 
+
+  .. option:: --verbose
+
+    Show verbose log
 
   .. note:: This file is designed for hierarchical PnR flow, which requires the tree of Multiple-Instanced-Blocks (MIBs).