From 977d81679dbf11c31639b52fc84b7c027bc88e73 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Oct 2021 17:23:10 -0700 Subject: [PATCH] [Engine] Upgrade check codes for WL CCFF --- .../src/check_circuit_library.cpp | 4 ++-- openfpga/src/base/openfpga_build_fabric.cpp | 1 + .../fabric/build_fabric_global_port_info.cpp | 10 ++++++++ .../fabric/build_fabric_global_port_info.h | 1 + .../src/fabric/fabric_global_port_info.cpp | 24 +++++++++++++++++++ openfpga/src/fabric/fabric_global_port_info.h | 8 +++++++ 6 files changed, 46 insertions(+), 2 deletions(-) diff --git a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp index 1a7eb60ed..0964cc10a 100644 --- a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp @@ -400,10 +400,10 @@ size_t check_wl_ccff_circuit_model_ports(const CircuitLibrary& circuit_lib, num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, CIRCUIT_MODEL_PORT_INPUT, num_input_ports, 1, false); - /* Check if we have a clock */ + /* Check if we have two clock: 1 for write-enable, 1 for shift register */ num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, CIRCUIT_MODEL_PORT_CLOCK, - 1, 1, true); + 2, 1, true); /* Check if we have 1 output*/ diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp index 1caac7342..211048eb3 100644 --- a/openfpga/src/base/openfpga_build_fabric.cpp +++ b/openfpga/src/base/openfpga_build_fabric.cpp @@ -124,6 +124,7 @@ int build_fabric(OpenfpgaContext& openfpga_ctx, /* Build fabric global port information */ openfpga_ctx.mutable_fabric_global_port_info() = build_fabric_global_port_info(openfpga_ctx.module_graph(), + openfpga_ctx.arch().config_protocol, openfpga_ctx.arch().tile_annotations, openfpga_ctx.arch().circuit_lib); diff --git a/openfpga/src/fabric/build_fabric_global_port_info.cpp b/openfpga/src/fabric/build_fabric_global_port_info.cpp index 2c745493a..d439a7fdf 100644 --- a/openfpga/src/fabric/build_fabric_global_port_info.cpp +++ b/openfpga/src/fabric/build_fabric_global_port_info.cpp @@ -24,6 +24,7 @@ namespace openfpga { * and cache their port/pin index in the top-level module *******************************************************************/ FabricGlobalPortInfo build_fabric_global_port_info(const ModuleManager& module_manager, + const ConfigProtocol& config_protocol, const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib) { vtr::ScopedStartFinishTimer timer("Create global port info for top module"); @@ -56,6 +57,15 @@ FabricGlobalPortInfo build_fabric_global_port_info(const ModuleManager& module_m fabric_global_port_info.set_global_port_is_shift_register(fabric_port, circuit_lib.port_is_shift_register(global_port)); fabric_global_port_info.set_global_port_is_config_enable(fabric_port, circuit_lib.port_is_config_enable(global_port)); fabric_global_port_info.set_global_port_default_value(fabric_port, circuit_lib.port_default_value(global_port)); + + /* Special for BL/WL shift register models: we should identify which clock belongs to BL and which clock belongs to WL */ + if (config_protocol.bl_memory_model() == circuit_lib.port_parent_model(global_port)) { + fabric_global_port_info.set_global_port_is_bl(fabric_port, true); + } + + if (config_protocol.wl_memory_model() == circuit_lib.port_parent_model(global_port)) { + fabric_global_port_info.set_global_port_is_wl(fabric_port, true); + } } /* Add the global ports from tile annotation */ diff --git a/openfpga/src/fabric/build_fabric_global_port_info.h b/openfpga/src/fabric/build_fabric_global_port_info.h index 5625d379f..6852a0249 100644 --- a/openfpga/src/fabric/build_fabric_global_port_info.h +++ b/openfpga/src/fabric/build_fabric_global_port_info.h @@ -19,6 +19,7 @@ namespace openfpga { FabricGlobalPortInfo build_fabric_global_port_info(const ModuleManager& module_manager, + const ConfigProtocol& config_protocol, const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib); diff --git a/openfpga/src/fabric/fabric_global_port_info.cpp b/openfpga/src/fabric/fabric_global_port_info.cpp index 60ef72d94..18108597d 100644 --- a/openfpga/src/fabric/fabric_global_port_info.cpp +++ b/openfpga/src/fabric/fabric_global_port_info.cpp @@ -55,6 +55,16 @@ bool FabricGlobalPortInfo::global_port_is_shift_register(const FabricGlobalPortI return global_port_is_shift_register_[global_port_id]; } +bool FabricGlobalPortInfo::global_port_is_bl(const FabricGlobalPortId& global_port_id) const { + VTR_ASSERT(valid_global_port_id(global_port_id)); + return global_port_is_bl_[global_port_id]; +} + +bool FabricGlobalPortInfo::global_port_is_wl(const FabricGlobalPortId& global_port_id) const { + VTR_ASSERT(valid_global_port_id(global_port_id)); + return global_port_is_wl_[global_port_id]; +} + bool FabricGlobalPortInfo::global_port_is_config_enable(const FabricGlobalPortId& global_port_id) const { VTR_ASSERT(valid_global_port_id(global_port_id)); return global_port_is_config_enable_[global_port_id]; @@ -83,6 +93,8 @@ FabricGlobalPortId FabricGlobalPortInfo::create_global_port(const ModulePortId& global_port_is_reset_.push_back(false); global_port_is_prog_.push_back(false); global_port_is_shift_register_.push_back(false); + global_port_is_bl_.push_back(false); + global_port_is_wl_.push_back(false); global_port_is_io_.push_back(false); global_port_is_config_enable_.push_back(false); global_port_default_values_.push_back(0); @@ -120,6 +132,18 @@ void FabricGlobalPortInfo::set_global_port_is_shift_register(const FabricGlobalP global_port_is_shift_register_[global_port_id] = is_shift_register; } +void FabricGlobalPortInfo::set_global_port_is_bl(const FabricGlobalPortId& global_port_id, + const bool& is_bl) { + VTR_ASSERT(valid_global_port_id(global_port_id)); + global_port_is_bl_[global_port_id] = is_bl; +} + +void FabricGlobalPortInfo::set_global_port_is_wl(const FabricGlobalPortId& global_port_id, + const bool& is_wl) { + VTR_ASSERT(valid_global_port_id(global_port_id)); + global_port_is_wl_[global_port_id] = is_wl; +} + void FabricGlobalPortInfo::set_global_port_is_config_enable(const FabricGlobalPortId& global_port_id, const bool& is_config_enable) { VTR_ASSERT(valid_global_port_id(global_port_id)); diff --git a/openfpga/src/fabric/fabric_global_port_info.h b/openfpga/src/fabric/fabric_global_port_info.h index 2521308d1..45f8f41cc 100644 --- a/openfpga/src/fabric/fabric_global_port_info.h +++ b/openfpga/src/fabric/fabric_global_port_info.h @@ -36,6 +36,8 @@ class FabricGlobalPortInfo { bool global_port_is_set(const FabricGlobalPortId& global_port_id) const; bool global_port_is_reset(const FabricGlobalPortId& global_port_id) const; bool global_port_is_prog(const FabricGlobalPortId& global_port_id) const; + bool global_port_is_bl(const FabricGlobalPortId& global_port_id) const; + bool global_port_is_wl(const FabricGlobalPortId& global_port_id) const; bool global_port_is_shift_register(const FabricGlobalPortId& global_port_id) const; bool global_port_is_config_enable(const FabricGlobalPortId& global_port_id) const; bool global_port_is_io(const FabricGlobalPortId& global_port_id) const; @@ -55,6 +57,10 @@ class FabricGlobalPortInfo { const bool& is_prog); void set_global_port_is_shift_register(const FabricGlobalPortId& global_port_id, const bool& is_shift_register); + void set_global_port_is_bl(const FabricGlobalPortId& global_port_id, + const bool& is_bl); + void set_global_port_is_wl(const FabricGlobalPortId& global_port_id, + const bool& is_wl); void set_global_port_is_config_enable(const FabricGlobalPortId& global_port_id, const bool& is_config_enable); void set_global_port_is_io(const FabricGlobalPortId& global_port_id, @@ -72,6 +78,8 @@ class FabricGlobalPortInfo { vtr::vector global_port_is_set_; vtr::vector global_port_is_prog_; vtr::vector global_port_is_shift_register_; + vtr::vector global_port_is_bl_; + vtr::vector global_port_is_wl_; vtr::vector global_port_is_config_enable_; vtr::vector global_port_is_io_; vtr::vector global_port_default_values_;