[doc] format

docs/source/dev_manual/cicd_setup.rst

@@ -44,7 +44,7 @@ in which case the docker image compiled for the latest master branch is used for
        ];
 
        RunRegression [
-           label = "Run functional regeression test"
+           label = "Run functional regression test"
            shape = box
        ];
 
@@ -69,7 +69,7 @@ in which case the docker image compiled for the latest master branch is used for
 
 .. option:: Build regression test
 
-    The OpenFPGA soure is compiled with the following set of compilers.
+    The OpenFPGA source is compiled with the following set of compilers.
 
       #. gcc-7
       #. gcc-8
@@ -81,9 +81,9 @@ in which case the docker image compiled for the latest master branch is used for
       #. clang-8
       #. clang-10
 
-    The docker images for these build enviroment are available on `github packages <https://github.com/orgs/lnis-uofu/packages>`_.
+    The docker images for these build environment are available on `github packages <https://github.com/orgs/lnis-uofu/packages>`_.
 
-.. option:: Functional regeression test
+.. option:: Functional regression test
 
     OpenFPGA maintains a set of functional tests to validate the different functionality.
     The test are broadly catagories into ``basic_reg_test``, ``fpga_verilog_reg_test``,
@@ -93,7 +93,7 @@ in which case the docker image compiled for the latest master branch is used for
 
 How to debug failed regression test
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-In case the ``funtional regression test`` fails,
+In case the ``functional regression test`` fails,
 the actions script will collect all ``.log`` files from
 the task directory and upload as a artifacts on github storage.
 These artifacts can be downloaded from the github website actions tab, for more reference follow `this <https://docs.github.com/en/actions/managing-workflow-runs/downloading-workflow-artifacts>`_ article.
@@ -113,11 +113,11 @@ Release Docker Images
 
 CI after cloning repository
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
-If you clone the repository the CI setup will still function, except the based images are  still pullled from "lnis-uofu" repsitory and the master branch
+If you clone the repository the CI setup will still function, except the based images are  still pulled from "lnis-uofu" repository and the master branch
 of cloned repo will not push final docker image to any repository .
 
-**In case you want to host your own copies of OpenFPGA base images** and final release create a githib secret variable with name  ``DOCKER_REPO`` and set it to ``true``. This will make ci script to download base images from your own repo pakcages, and upload final realse to the same.
+**In case you want to host your own copies of OpenFPGA base images** and final release create a github secret variable with name  ``DOCKER_REPO`` and set it to ``true``. This will make ci script to download base images from your own repo packages, and upload final release to the same.
 
-**If you don not want to use docker images based regression test** and like to compile all the bianries for each CI run. You can set ``IGNORE_DOCKER_TEST`` secrete variable to ``true``.
+**If you don not want to use docker images based regression test** and like to compile all the binaries for each CI run. You can set ``IGNORE_DOCKER_TEST`` secrete variable to ``true``.
 
-.. note:: Once you add ``DOCKER_REPO`` variable, you need to genrerate base images. To do this trigger mannual workflow ``Build docker CI images``
+.. note:: Once you add ``DOCKER_REPO`` variable, you need to generate base images. To do this trigger manual workflow ``Build docker CI images``

docs/source/manual/file_formats/fabric_bitstream.rst

@@ -11,7 +11,7 @@ Plain text (.bit)
 This file format is designed to be directly loaded to an FPGA fabric.
 It does not include any comments but only bitstream.
 
-The information depends on the type of configuration procotol.
+The information depends on the type of configuration protocol.
 
 .. option:: vanilla
 
@@ -232,7 +232,7 @@ A quick example:
   <bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
   </bit>
 
-Other information may depend on the type of configuration procotol.
+Other information may depend on the type of configuration protocol.
 
 .. option:: memory_bank
 

docs/source/manual/file_formats/index.rst

@@ -1,7 +1,7 @@
 File Formats
 ------------
 
-OpenFPGA widely uses XML format for interchangable files
+OpenFPGA widely uses XML format for interchangeable files
 
 
 .. _file_formats:

docs/source/manual/fpga_verilog/testbench.rst

@@ -37,7 +37,7 @@ To enable self-testing, the FPGA and user's RTL design (simulate using an HDL si
 
 Full Testbench
 ~~~~~~~~~~~~~~
-Full testbench aims at simulating an entire FPGA operating period, consisting of two phases: 
+Full testbench aims at simulating an entire FPGA operating period, consisting of two phases:
 
   - the **Configuration Phase**, where the synthesized design bitstream is loaded to the programmable fabric, as highlighted by the green rectangle of :numref:`fig_verilog_full_testbench_waveform`;
 
@@ -63,7 +63,7 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
 
    Hierarchy of Verilog testbenches for a FPGA fabric implemented with an application
 
-.. note:: ``<bench_name>`` is the module name of users' RTL design. 
+.. note:: ``<bench_name>`` is the module name of users' RTL design.
 
 .. option:: <bench_name>_include_netlist.v
 
@@ -84,9 +84,9 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
 .. option:: <bench_name>_top_formal_verification.v
 
   This netlist includes a Verilog module of a pre-configured FPGA fabric, which is a wrapper on top of the ``fpga_top.v`` netlist.
-  The wrapper module has the same port map as the top-level module of user's RTL design, which be directly def to formal verification tools to validate FPGA's functional equivalence. 
+  The wrapper module has the same port map as the top-level module of user's RTL design, which be directly def to formal verification tools to validate FPGA's functional equivalence.
   :numref:`fig_preconfig_module` illustrates the organization of a pre-configured module, which consists of a FPGA fabric (see :ref:`fabric_netlists`) and a hard-coded bitstream.
-  Only used I/Os of FPGA fabric will appear in the port list of the pre-configured module. 
+  Only used I/Os of FPGA fabric will appear in the port list of the pre-configured module.
 
 .. _fig_preconfig_module:
 
@@ -94,4 +94,3 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
    :width: 100%
 
    Internal structure of a pre-configured FPGA module
-