[core] syntax

This commit is contained in:
tangxifan 2023-09-25 16:50:30 -07:00
parent ca715f4c82
commit 96f36a96dd
3 changed files with 7 additions and 6 deletions

View File

@ -20,6 +20,7 @@ set_target_properties(libarchopenfpga PROPERTIES PREFIX "") #Avoid extra 'lib' p
#Specify link-time dependancies
target_link_libraries(libarchopenfpga
libopenfpgautil
libopenfpgashell
libvtrutil
libarchfpga
libpugiutil)

View File

@ -23,7 +23,7 @@ TileAnnotation::global_port_range TileAnnotation::global_ports() const {
return vtr::make_range(global_port_ids_.begin(), global_port_ids_.end());
}
std::vector<std::string> tiles_to_merge_ports() const {
std::vector<std::string> TileAnnotation::tiles_to_merge_ports() const {
std::vector<std::string> tile_names;
for (auto it = tile_ports_to_merge_.begin(); it != tile_ports_to_merge_.end(); it++) {
tile_names.push_back(it->first);
@ -31,14 +31,14 @@ std::vector<std::string> tiles_to_merge_ports() const {
return tile_names;
}
std::vector<std::string> tile_ports_to_merge(const std::string& tile_name) const {
std::vector<std::string> TileAnnotation::tile_ports_to_merge(const std::string& tile_name) const {
std::vector<std::string> port_names;
const auto& result = tile_ports_to_merge_.find(tile_name);
if (result == tile_ports_to_merge.end()) {
if (result == tile_ports_to_merge_.end()) {
VTR_LOG_WARN("Tile '%s' does not contain any ports to merge!\n", tile_name.c_str());
return port_names;
}
return result.second;
return result->second;
}
/************************************************************************
@ -206,7 +206,7 @@ int TileAnnotation::add_merge_subtile_ports(const std::string& tile_name, const
tile_ports_to_merge_[tile_name].push_back(port_name);
} else {
/* Check if the port name is already in the list, if yes, error out */
if (result->second.end() == std::find(result->secnd.begin(), result->second.end(), port_name)) {
if (result->second.end() == std::find(result->second.begin(), result->second.end(), port_name)) {
tile_ports_to_merge_[tile_name].push_back(port_name);
} else {
VTR_LOG_ERROR("Port '%s' has already been defined twice for tile '%s' to be merged!", port_name.c_str(), tile_name.c_str());

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@ -36,7 +36,7 @@ static std::vector<std::string> format_argv(const std::string& cmd_name,
* We want a renamed version for fabric B is
* <module_name default="tile_2__2_" given="tile_big"/>
*/
int rename_module_names_for_fabricB_from_fabricA(
static int rename_module_names_for_fabricB_from_fabricA(
const openfpga::ModuleNameMap& refA_module_names,
const openfpga::ModuleNameMap& renamedA_module_names,
const openfpga::ModuleNameMap& refB_module_names,