From 9655bc35cb2b5829abdaac50ca2889a5b40ed7be Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 29 Jun 2021 17:04:19 -0600
Subject: [PATCH] [Script] Bug fix due to the full testbench generation changes

---
 .../generate_testbench_example_script.openfpga                  | 2 --
 1 file changed, 2 deletions(-)

diff --git a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga
index b0322f105..0b5cfa232 100644
--- a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga
@@ -52,8 +52,6 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} 
 
 # Write the SDC to run timing analysis for a mapped FPGA fabric
 write_analysis_sdc --file ./SDC_analysis