Update test
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@ -16,7 +16,7 @@ run-task fpga_bitstream/generate_bitstream/configuration_chain/device_48x48 $@
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run-task fpga_bitstream/generate_bitstream/ql_memory_bank_shift_register/device_48x48 $@
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echo -e "Testing bitstream generation for an 4x4 FPGA device (overwrite IO tile bits)";
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run-task fpga_bitstream/generate_bitstream/configuration_chain/device_4x4_overwrite $@
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run-task fpga_bitstream/generate_bitstream/configuration_chain/device_4x4_PathBitSetting $@
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echo -e "Testing bitstream generation for an 96x96 FPGA device";
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run-task fpga_bitstream/generate_bitstream/configuration_chain/device_96x96 $@
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@ -0,0 +1,9 @@
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<!--
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////////////////////////////////////////////////////////////////////////////////
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# THIS FILE WAS AUTOMATICALLY GENERATED FROM DO NOT EDIT
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////////////////////////////////////////////////////////////////////////////////
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-->
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<openfpga_bitstream_setting>
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<bit value="0" path="fpga_top.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem[0]"/>
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<bit value="1" path="fpga_top.grid_io_bottom_3__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem[0]"/>
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</openfpga_bitstream_setting>
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@ -16,9 +16,10 @@ timeout_each_job = 20*60
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fpga_flow=vpr_blif
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script_overwrite.openfpga
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/configuration_chain/device_4x4_PathBitSetting/config/write_xml.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/configuration_chain/device_4x4_PathBitSetting/config/bitstream_annotation.xml
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openfpga_vpr_device_layout=4x4
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[ARCHITECTURES]
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@ -1,3 +1,5 @@
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# This file is copied from fix_device_example_script.openfpga
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# Run VPR for the 'and' design
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#--write_rr_graph example_rr_graph.xml
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
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@ -8,6 +10,9 @@ read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Read OpenFPGA bitstream settings
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read_openfpga_bitstream_setting -f ${OPENFPGA_BITSTREAM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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@ -34,7 +39,7 @@ repack #--verbose
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# Build the bitstream
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# - Output the fabric-independent bitstream to a file
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build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml --overwrite_bitstream_file ../../../../config/overwrite_bitstream.txt
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build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
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# Build fabric-dependent bitstream
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build_fabric_bitstream --verbose
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@ -1,2 +0,0 @@
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fpga_top.grid_io_left_0__1_ logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem 0
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fpga_top.grid_io_bottom_3__0_ logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem [0]=0
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