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clean up the sample arch

This commit is contained in:
tangxifan 2020-01-16 20:52:47 -07:00
parent a598929fe7
commit 95edd3c091
2 changed files with 42 additions and 36 deletions
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71
libopenfpga/libarchopenfpga/arch/sample_arch.xml
View File

@ -9,14 +9,17 @@
--> -->
<openfpga_architecture> <openfpga_architecture>
<technology> <technology>
<library lib_type="academia" transistor_type="TOP_TT" lib_path="OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/> <library type="academia" corner="TOP_TT" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<transistors pn_ratio="2" model_ref="M"> <logic_transistors pn_ratio="2" model_ref="M" vdd="0.9">
<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/> <nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/> <pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
<io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/> </logic_transistors>
<io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/> <io_transistors pn_ratio="2" model_ref="M" vdd="2.5">
</transistors> <nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
<rram model_name="rram" rlrs="5e3" rhrs="20e6"/> <pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
</io_transistors>
<rram model_name="rram_mem" rlrs="1e4" rhrs="1e5"/>
<rram model_name="rram_logic" rlrs="5e3" rhrs="20e6"/>
</technology> </technology>
<circuit_library> <circuit_library>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true"> <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
@ -234,32 +237,30 @@
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
</openfpga_architecture> </openfpga_architecture>
<openfpga_verification> <openfpga_simulation_setting>
<simulation_parameters> <general sim_temp="25" post="false" captab="false" fast="true"/>
<options sim_temp="25" post="off" captab="off" fast="on"/> <monte_carlo mc_sim="false" num_mc_points="2" cmos_variation="false" rram_variation="false">
<monte_carlo mc_sim="off" num_mc_points="2" cmos_variation="off" rram_variation="off"> <cmos abs_variation="0.1" num_sigma="3"/>
<cmos abs_variation="0.1" num_sigma="3"/> <rram abs_variation="0.1" num_sigma="3"/>
<rram abs_variation="0.1" num_sigma="3"/> </monte_carlo>
</monte_carlo> <measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs"> <slew>
<slew> <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/> <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/> </slew>
</slew> <delay>
<delay> <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
<rise input_thres_pct="0.5" output_thres_pct="0.5"/> <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/> </delay>
</delay> </measure>
</measure> <stimuli>
<stimuli> <clock op_freq="200e6" sim_slack="0.2" prog_freq="10e6">
<clock op_freq="200e6" sim_slack="0.2" prog_freq="10e6"> <rise slew_time="20e-12" slew_type="abs"/>
<rise slew_time="20e-12" slew_type="abs"/> <fall slew_time="20e-12" slew_type="abs"/>
<fall slew_time="20e-12" slew_type="abs"/> </clock>
</clock> <input>
<input> <rise slew_time="25e-12" slew_type="abs"/>
<rise slew_time="25e-12" slew_type="abs"/> <fall slew_time="25e-12" slew_type="abs"/>
<fall slew_time="25e-12" slew_type="abs"/> </input>
</input> </stimuli>
</stimuli> </openfpga_simulation_setting>
</simulation_parameters>
</openfpga_verification>

7
libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
View File

@ -32,7 +32,7 @@ openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name) {
try { try {
loc_data = pugiutil::load_xml(doc, arch_file_name); loc_data = pugiutil::load_xml(doc, arch_file_name);
/* Root node should be <circuit_settings> */ /* First node should be <openfpga_architecture> */
auto xml_circuit_settings = get_single_child(doc, "openfpga_architecture", loc_data); auto xml_circuit_settings = get_single_child(doc, "openfpga_architecture", loc_data);
/* Parse circuit_models to circuit library /* Parse circuit_models to circuit library
@ -47,6 +47,11 @@ openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name) {
/* Build the timing graph inside the circuit library */ /* Build the timing graph inside the circuit library */
openfpga_arch.circuit_lib.build_timing_graphs(); openfpga_arch.circuit_lib.build_timing_graphs();
/* Second node should be <openfpga_simulation_setting> */
auto xml_simulation_settings = get_single_child(doc, "openfpga_simulation_setting", loc_data);
/* Parse simulation settings to data structure */
} catch (pugiutil::XmlError& e) { } catch (pugiutil::XmlError& e) {
archfpga_throw(arch_file_name, e.line(), archfpga_throw(arch_file_name, e.line(),
"%s", e.what()); "%s", e.what());