move refactored Verilog routing block generation functions to cpp files
This commit is contained in:
tangxifan
parent
322228de43
commit
95ea513339
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@ -3843,338 +3843,3 @@ void print_verilog_routing_resources(ModuleManager& module_manager,
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return;
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}
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/********************************************************************
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* Print the sub-circuit of a connection Box (Type: [CHANX|CHANY])
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* Actually it is very similiar to switch box but
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* the difference is connection boxes connect Grid INPUT Pins to channels
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* NOTE: direct connection between CLBs should NOT be included inside this
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* module! They should be added in the top-level module as their connection
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* is not limited to adjacent CLBs!!!
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*
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* Location of a X- and Y-direction Connection Block in FPGA fabric
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* +------------+ +-------------+
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* | |------>| |
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* | CLB |<------| Y-direction |
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* | | ... | Connection |
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* | |------>| Block |
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* +------------+ +-------------+
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* | ^ ... | | ^ ... |
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* v | v v | v
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* +-------------------+ +-------------+
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* --->| |--->| |
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* <---| X-direction |<---| Switch |
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* ...| Connection block |... | Block |
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* --->| |--->| |
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* +-------------------+ +-------------+
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*
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* Internal structure:
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* This is an example of a X-direction connection block
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* Note that middle output ports are shorted wire from inputs of routing tracks,
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* which are also the inputs of routing multiplexer of the connection block
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*
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* CLB Input Pins
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* (IPINs)
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* ^ ^ ^
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* | | ... |
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* +--------------------------+
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* | ^ ^ ^ |
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* | | | ... | |
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* | +--------------------+ |
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* | | routing | |
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* | | multiplexers | |
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* | +--------------------+ |
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* | middle outputs |
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* | of routing channel |
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* | ^ ^ ^ ^ ^ ^ ^ ^ |
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* | | | | | ... | | | | |
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* in[0] -->|------------------------->|---> out[0]
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* out[1] <--|<-------------------------|<--- in[1]
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* | ... |
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* in[W-2] -->|------------------------->|---> out[W-2]
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* out[W-1] <--|<-------------------------|<--- in[W-1]
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* +--------------------------+
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*
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* W: routing channel width
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*
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********************************************************************/
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static
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void print_verilog_routing_connection_box_unique_module(ModuleManager& module_manager,
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const std::string& verilog_dir,
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const std::string& subckt_dir,
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const RRGSB& rr_gsb,
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const t_rr_type& cb_type,
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const bool& use_explicit_port_map) {
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/* Create the netlist */
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vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
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std::string verilog_fname(subckt_dir + generate_connection_block_netlist_name(cb_type, gsb_coordinate, std::string(verilog_netlist_file_postfix)));
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/* TODO: remove the bak file when the file is ready */
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//verilog_fname += ".bak";
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/* Create the file stream */
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std::fstream fp;
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fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
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check_file_handler(fp);
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print_verilog_file_header(fp, std::string("Verilog modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]"));
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/* Print preprocessing flags */
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print_verilog_include_defines_preproc_file(fp, verilog_dir);
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/* Create a Verilog Module based on the circuit model, and add to module manager */
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ModuleId cb_module = module_manager.find_module(generate_connection_block_module_name(cb_type, gsb_coordinate));
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VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
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/* Write the verilog module */
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write_verilog_module_to_file(fp, module_manager, cb_module, use_explicit_port_map);
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/* Add an empty line as a splitter */
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fp << std::endl;
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/* Close file handler */
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fp.close();
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/* Add fname to the linked list */
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routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str());
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}
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/*********************************************************************
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* Generate the Verilog module for a Switch Box.
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* A Switch Box module consists of following ports:
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* 1. Channel Y [x][y] inputs
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* 2. Channel X [x+1][y] inputs
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* 3. Channel Y [x][y-1] outputs
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* 4. Channel X [x][y] outputs
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* 5. Grid[x][y+1] Right side outputs pins
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* 6. Grid[x+1][y+1] Left side output pins
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* 7. Grid[x+1][y+1] Bottom side output pins
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* 8. Grid[x+1][y] Top side output pins
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* 9. Grid[x+1][y] Left side output pins
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* 10. Grid[x][y] Right side output pins
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* 11. Grid[x][y] Top side output pins
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* 12. Grid[x][y+1] Bottom side output pins
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*
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* Location of a Switch Box in FPGA fabric:
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*
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* -------------- --------------
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* | | | |
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* | Grid | ChanY | Grid |
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* | [x][y+1] | [x][y+1] | [x+1][y+1] |
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* | | | |
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* -------------- --------------
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* ----------
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* ChanX | Switch | ChanX
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* [x][y] | Box | [x+1][y]
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* | [x][y] |
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* ----------
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* -------------- --------------
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* | | | |
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* | Grid | ChanY | Grid |
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* | [x][y] | [x][y] | [x+1][y] |
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* | | | |
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* -------------- --------------
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*
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* Switch Block pin location map
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*
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* Grid[x][y+1] ChanY[x][y+1] Grid[x+1][y+1]
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* right_pins inputs/outputs left_pins
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* | ^ |
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* | | |
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* v v v
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* +-----------------------------------------------+
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* | |
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* Grid[x][y+1] | | Grid[x+1][y+1]
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* bottom_pins---->| |<---- bottom_pins
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* | |
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* ChanX[x][y] | Switch Box [x][y] | ChanX[x+1][y]
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* inputs/outputs<--->| |<---> inputs/outputs
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* | |
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* Grid[x][y+1] | | Grid[x+1][y+1]
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* top_pins---->| |<---- top_pins
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* | |
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* +-----------------------------------------------+
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* ^ ^ ^
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* | | |
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* | v |
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* Grid[x][y] ChanY[x][y] Grid[x+1][y]
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* right_pins inputs/outputs left_pins
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*
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*
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********************************************************************/
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static
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void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manager,
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const std::string& verilog_dir,
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const std::string& subckt_dir,
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const RRGSB& rr_gsb,
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const bool& use_explicit_port_map) {
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/* Create the netlist */
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vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
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std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(sb_verilog_file_name_prefix, gsb_coordinate, std::string(verilog_netlist_file_postfix)));
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/* TODO: remove the bak file when the file is ready */
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//verilog_fname += ".bak";
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/* Create the file stream */
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std::fstream fp;
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fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
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check_file_handler(fp);
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print_verilog_file_header(fp, std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]"));
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/* Print preprocessing flags */
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print_verilog_include_defines_preproc_file(fp, verilog_dir);
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/* Create a Verilog Module based on the circuit model, and add to module manager */
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ModuleId sb_module = module_manager.find_module(generate_switch_block_module_name(gsb_coordinate));
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VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
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/* Write the verilog module */
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write_verilog_module_to_file(fp, module_manager, sb_module, use_explicit_port_map);
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/* Close file handler */
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fp.close();
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/* Add fname to the linked list */
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routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str());
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return;
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}
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/********************************************************************
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* Iterate over all the connection blocks in a device
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* and build a module for each of them
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*******************************************************************/
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static
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void print_verilog_flatten_connection_block_modules(ModuleManager& module_manager,
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const DeviceRRGSB& L_device_rr_gsb,
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const std::string& verilog_dir,
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const std::string& subckt_dir,
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const t_rr_type& cb_type,
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const bool& use_explicit_port_map) {
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/* Build unique X-direction connection block modules */
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DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range();
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for (size_t ix = 0; ix < cb_range.get_x(); ++ix) {
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for (size_t iy = 0; iy < cb_range.get_y(); ++iy) {
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/* Check if the connection block exists in the device!
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* Some of them do NOT exist due to heterogeneous blocks (height > 1)
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* We will skip those modules
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*/
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const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy);
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if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)))
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|| (true != rr_gsb.is_cb_exist(cb_type))) {
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continue;
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}
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print_verilog_routing_connection_box_unique_module(module_manager,
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verilog_dir,
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subckt_dir,
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rr_gsb, cb_type,
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use_explicit_port_map);
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}
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}
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}
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/********************************************************************
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* A top-level function of this file
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* Print all the modules for global routing architecture of a FPGA fabric
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* in Verilog format in a flatten way:
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* Each connection block and switch block will be generated as a unique module
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* Covering:
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* 1. Connection blocks
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* 2. Switch blocks
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*******************************************************************/
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void print_verilog_flatten_routing_modules(ModuleManager& module_manager,
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const DeviceRRGSB& L_device_rr_gsb,
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const t_det_routing_arch& routing_arch,
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const std::string& verilog_dir,
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const std::string& subckt_dir,
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const bool& use_explicit_port_map) {
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/* We only support uni-directional routing architecture now */
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VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality);
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/* TODO: deprecate DeviceCoordinator, use vtr::Point<size_t> only! */
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DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range();
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/* Build unique switch block modules */
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for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
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for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
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const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy);
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print_verilog_routing_switch_box_unique_module(module_manager,
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verilog_dir,
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subckt_dir,
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rr_gsb,
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use_explicit_port_map);
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}
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}
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print_verilog_flatten_connection_block_modules(module_manager, L_device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map);
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print_verilog_flatten_connection_block_modules(module_manager, L_device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map);
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vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n");
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dump_verilog_subckt_header_file(routing_verilog_subckt_file_path_head,
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subckt_dir.c_str(),
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routing_verilog_file_name);
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}
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/********************************************************************
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* A top-level function of this file
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* Print all the unique modules for global routing architecture of a FPGA fabric
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* in Verilog format, including:
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* 1. Connection blocks
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* 2. Switch blocks
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*
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* Note: this function SHOULD be called only when
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* the option compact_routing_hierarchy is turned on!!!
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*******************************************************************/
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void print_verilog_unique_routing_modules(ModuleManager& module_manager,
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const DeviceRRGSB& L_device_rr_gsb,
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const t_det_routing_arch& routing_arch,
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const std::string& verilog_dir,
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const std::string& subckt_dir,
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const bool& use_explicit_port_map) {
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/* We only support uni-directional routing architecture now */
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VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality);
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/* Build unique switch block modules */
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for (size_t isb = 0; isb < L_device_rr_gsb.get_num_sb_unique_module(); ++isb) {
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const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(isb);
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print_verilog_routing_switch_box_unique_module(module_manager,
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verilog_dir,
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subckt_dir,
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unique_mirror,
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use_explicit_port_map);
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}
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/* Build unique X-direction connection block modules */
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for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) {
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const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANX, icb);
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print_verilog_routing_connection_box_unique_module(module_manager,
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verilog_dir,
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subckt_dir,
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unique_mirror, CHANX,
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use_explicit_port_map);
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}
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/* Build unique X-direction connection block modules */
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for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
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const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANY, icb);
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print_verilog_routing_connection_box_unique_module(module_manager,
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verilog_dir,
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subckt_dir,
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unique_mirror, CHANY,
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use_explicit_port_map);
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}
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vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n");
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dump_verilog_subckt_header_file(routing_verilog_subckt_file_path_head,
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subckt_dir.c_str(),
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routing_verilog_file_name);
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}
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@ -0,0 +1,351 @@
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/*********************************************************************
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* This file includes functions that are used for
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* Verilog generation of FPGA routing architecture (global routing)
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*********************************************************************/
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#include <time.h>
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#include "vtr_assert.h"
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/* Include FPGA-X2P header files*/
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#include "fpga_x2p_naming.h"
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#include "fpga_x2p_utils.h"
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/* Include FPGA-Verilog header files*/
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#include "verilog_global.h"
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#include "verilog_utils.h"
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#include "verilog_writer_utils.h"
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#include "verilog_module_writer.h"
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#include "verilog_routing.h"
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/********************************************************************
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* Print the sub-circuit of a connection Box (Type: [CHANX|CHANY])
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* Actually it is very similiar to switch box but
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* the difference is connection boxes connect Grid INPUT Pins to channels
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* NOTE: direct connection between CLBs should NOT be included inside this
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* module! They should be added in the top-level module as their connection
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* is not limited to adjacent CLBs!!!
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*
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* Location of a X- and Y-direction Connection Block in FPGA fabric
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* +------------+ +-------------+
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* | |------>| |
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* | CLB |<------| Y-direction |
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* | | ... | Connection |
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* | |------>| Block |
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* +------------+ +-------------+
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* | ^ ... | | ^ ... |
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* v | v v | v
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* +-------------------+ +-------------+
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* --->| |--->| |
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* <---| X-direction |<---| Switch |
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* ...| Connection block |... | Block |
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* --->| |--->| |
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* +-------------------+ +-------------+
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*
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* Internal structure:
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* This is an example of a X-direction connection block
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* Note that middle output ports are shorted wire from inputs of routing tracks,
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* which are also the inputs of routing multiplexer of the connection block
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*
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* CLB Input Pins
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* (IPINs)
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* ^ ^ ^
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* | | ... |
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* +--------------------------+
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* | ^ ^ ^ |
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* | | | ... | |
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* | +--------------------+ |
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* | | routing | |
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* | | multiplexers | |
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* | +--------------------+ |
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* | middle outputs |
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* | of routing channel |
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* | ^ ^ ^ ^ ^ ^ ^ ^ |
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* | | | | | ... | | | | |
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* in[0] -->|------------------------->|---> out[0]
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* out[1] <--|<-------------------------|<--- in[1]
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* | ... |
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* in[W-2] -->|------------------------->|---> out[W-2]
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* out[W-1] <--|<-------------------------|<--- in[W-1]
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* +--------------------------+
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*
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* W: routing channel width
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*
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********************************************************************/
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static
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void print_verilog_routing_connection_box_unique_module(ModuleManager& module_manager,
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const std::string& verilog_dir,
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const std::string& subckt_dir,
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const RRGSB& rr_gsb,
|
||||
const t_rr_type& cb_type,
|
||||
const bool& use_explicit_port_map) {
|
||||
/* Create the netlist */
|
||||
vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
|
||||
std::string verilog_fname(subckt_dir + generate_connection_block_netlist_name(cb_type, gsb_coordinate, std::string(verilog_netlist_file_postfix)));
|
||||
/* TODO: remove the bak file when the file is ready */
|
||||
//verilog_fname += ".bak";
|
||||
|
||||
/* Create the file stream */
|
||||
std::fstream fp;
|
||||
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
|
||||
|
||||
check_file_handler(fp);
|
||||
|
||||
print_verilog_file_header(fp, std::string("Verilog modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]"));
|
||||
|
||||
/* Print preprocessing flags */
|
||||
print_verilog_include_defines_preproc_file(fp, verilog_dir);
|
||||
|
||||
/* Create a Verilog Module based on the circuit model, and add to module manager */
|
||||
ModuleId cb_module = module_manager.find_module(generate_connection_block_module_name(cb_type, gsb_coordinate));
|
||||
VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
|
||||
|
||||
/* Write the verilog module */
|
||||
write_verilog_module_to_file(fp, module_manager, cb_module, use_explicit_port_map);
|
||||
|
||||
/* Add an empty line as a splitter */
|
||||
fp << std::endl;
|
||||
|
||||
/* Close file handler */
|
||||
fp.close();
|
||||
|
||||
/* Add fname to the linked list */
|
||||
routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str());
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* Generate the Verilog module for a Switch Box.
|
||||
* A Switch Box module consists of following ports:
|
||||
* 1. Channel Y [x][y] inputs
|
||||
* 2. Channel X [x+1][y] inputs
|
||||
* 3. Channel Y [x][y-1] outputs
|
||||
* 4. Channel X [x][y] outputs
|
||||
* 5. Grid[x][y+1] Right side outputs pins
|
||||
* 6. Grid[x+1][y+1] Left side output pins
|
||||
* 7. Grid[x+1][y+1] Bottom side output pins
|
||||
* 8. Grid[x+1][y] Top side output pins
|
||||
* 9. Grid[x+1][y] Left side output pins
|
||||
* 10. Grid[x][y] Right side output pins
|
||||
* 11. Grid[x][y] Top side output pins
|
||||
* 12. Grid[x][y+1] Bottom side output pins
|
||||
*
|
||||
* Location of a Switch Box in FPGA fabric:
|
||||
*
|
||||
* -------------- --------------
|
||||
* | | | |
|
||||
* | Grid | ChanY | Grid |
|
||||
* | [x][y+1] | [x][y+1] | [x+1][y+1] |
|
||||
* | | | |
|
||||
* -------------- --------------
|
||||
* ----------
|
||||
* ChanX | Switch | ChanX
|
||||
* [x][y] | Box | [x+1][y]
|
||||
* | [x][y] |
|
||||
* ----------
|
||||
* -------------- --------------
|
||||
* | | | |
|
||||
* | Grid | ChanY | Grid |
|
||||
* | [x][y] | [x][y] | [x+1][y] |
|
||||
* | | | |
|
||||
* -------------- --------------
|
||||
*
|
||||
* Switch Block pin location map
|
||||
*
|
||||
* Grid[x][y+1] ChanY[x][y+1] Grid[x+1][y+1]
|
||||
* right_pins inputs/outputs left_pins
|
||||
* | ^ |
|
||||
* | | |
|
||||
* v v v
|
||||
* +-----------------------------------------------+
|
||||
* | |
|
||||
* Grid[x][y+1] | | Grid[x+1][y+1]
|
||||
* bottom_pins---->| |<---- bottom_pins
|
||||
* | |
|
||||
* ChanX[x][y] | Switch Box [x][y] | ChanX[x+1][y]
|
||||
* inputs/outputs<--->| |<---> inputs/outputs
|
||||
* | |
|
||||
* Grid[x][y+1] | | Grid[x+1][y+1]
|
||||
* top_pins---->| |<---- top_pins
|
||||
* | |
|
||||
* +-----------------------------------------------+
|
||||
* ^ ^ ^
|
||||
* | | |
|
||||
* | v |
|
||||
* Grid[x][y] ChanY[x][y] Grid[x+1][y]
|
||||
* right_pins inputs/outputs left_pins
|
||||
*
|
||||
*
|
||||
********************************************************************/
|
||||
static
|
||||
void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manager,
|
||||
const std::string& verilog_dir,
|
||||
const std::string& subckt_dir,
|
||||
const RRGSB& rr_gsb,
|
||||
const bool& use_explicit_port_map) {
|
||||
/* Create the netlist */
|
||||
vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
|
||||
std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(sb_verilog_file_name_prefix, gsb_coordinate, std::string(verilog_netlist_file_postfix)));
|
||||
/* TODO: remove the bak file when the file is ready */
|
||||
//verilog_fname += ".bak";
|
||||
|
||||
/* Create the file stream */
|
||||
std::fstream fp;
|
||||
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
|
||||
|
||||
check_file_handler(fp);
|
||||
|
||||
print_verilog_file_header(fp, std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]"));
|
||||
|
||||
/* Print preprocessing flags */
|
||||
print_verilog_include_defines_preproc_file(fp, verilog_dir);
|
||||
|
||||
/* Create a Verilog Module based on the circuit model, and add to module manager */
|
||||
ModuleId sb_module = module_manager.find_module(generate_switch_block_module_name(gsb_coordinate));
|
||||
VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
|
||||
|
||||
/* Write the verilog module */
|
||||
write_verilog_module_to_file(fp, module_manager, sb_module, use_explicit_port_map);
|
||||
|
||||
/* Close file handler */
|
||||
fp.close();
|
||||
|
||||
/* Add fname to the linked list */
|
||||
routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str());
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/********************************************************************
|
||||
* Iterate over all the connection blocks in a device
|
||||
* and build a module for each of them
|
||||
*******************************************************************/
|
||||
static
|
||||
void print_verilog_flatten_connection_block_modules(ModuleManager& module_manager,
|
||||
const DeviceRRGSB& L_device_rr_gsb,
|
||||
const std::string& verilog_dir,
|
||||
const std::string& subckt_dir,
|
||||
const t_rr_type& cb_type,
|
||||
const bool& use_explicit_port_map) {
|
||||
/* Build unique X-direction connection block modules */
|
||||
DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range();
|
||||
|
||||
for (size_t ix = 0; ix < cb_range.get_x(); ++ix) {
|
||||
for (size_t iy = 0; iy < cb_range.get_y(); ++iy) {
|
||||
/* Check if the connection block exists in the device!
|
||||
* Some of them do NOT exist due to heterogeneous blocks (height > 1)
|
||||
* We will skip those modules
|
||||
*/
|
||||
const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy);
|
||||
if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)))
|
||||
|| (true != rr_gsb.is_cb_exist(cb_type))) {
|
||||
continue;
|
||||
}
|
||||
print_verilog_routing_connection_box_unique_module(module_manager,
|
||||
verilog_dir,
|
||||
subckt_dir,
|
||||
rr_gsb, cb_type,
|
||||
use_explicit_port_map);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/********************************************************************
|
||||
* A top-level function of this file
|
||||
* Print all the modules for global routing architecture of a FPGA fabric
|
||||
* in Verilog format in a flatten way:
|
||||
* Each connection block and switch block will be generated as a unique module
|
||||
* Covering:
|
||||
* 1. Connection blocks
|
||||
* 2. Switch blocks
|
||||
*******************************************************************/
|
||||
void print_verilog_flatten_routing_modules(ModuleManager& module_manager,
|
||||
const DeviceRRGSB& L_device_rr_gsb,
|
||||
const t_det_routing_arch& routing_arch,
|
||||
const std::string& verilog_dir,
|
||||
const std::string& subckt_dir,
|
||||
const bool& use_explicit_port_map) {
|
||||
/* We only support uni-directional routing architecture now */
|
||||
VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality);
|
||||
|
||||
/* TODO: deprecate DeviceCoordinator, use vtr::Point<size_t> only! */
|
||||
DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range();
|
||||
|
||||
/* Build unique switch block modules */
|
||||
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
|
||||
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
|
||||
const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy);
|
||||
print_verilog_routing_switch_box_unique_module(module_manager,
|
||||
verilog_dir,
|
||||
subckt_dir,
|
||||
rr_gsb,
|
||||
use_explicit_port_map);
|
||||
}
|
||||
}
|
||||
|
||||
print_verilog_flatten_connection_block_modules(module_manager, L_device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map);
|
||||
|
||||
print_verilog_flatten_connection_block_modules(module_manager, L_device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map);
|
||||
|
||||
vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n");
|
||||
dump_verilog_subckt_header_file(routing_verilog_subckt_file_path_head,
|
||||
subckt_dir.c_str(),
|
||||
routing_verilog_file_name);
|
||||
}
|
||||
|
||||
|
||||
/********************************************************************
|
||||
* A top-level function of this file
|
||||
* Print all the unique modules for global routing architecture of a FPGA fabric
|
||||
* in Verilog format, including:
|
||||
* 1. Connection blocks
|
||||
* 2. Switch blocks
|
||||
*
|
||||
* Note: this function SHOULD be called only when
|
||||
* the option compact_routing_hierarchy is turned on!!!
|
||||
*******************************************************************/
|
||||
void print_verilog_unique_routing_modules(ModuleManager& module_manager,
|
||||
const DeviceRRGSB& L_device_rr_gsb,
|
||||
const t_det_routing_arch& routing_arch,
|
||||
const std::string& verilog_dir,
|
||||
const std::string& subckt_dir,
|
||||
const bool& use_explicit_port_map) {
|
||||
/* We only support uni-directional routing architecture now */
|
||||
VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality);
|
||||
|
||||
/* Build unique switch block modules */
|
||||
for (size_t isb = 0; isb < L_device_rr_gsb.get_num_sb_unique_module(); ++isb) {
|
||||
const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(isb);
|
||||
print_verilog_routing_switch_box_unique_module(module_manager,
|
||||
verilog_dir,
|
||||
subckt_dir,
|
||||
unique_mirror,
|
||||
use_explicit_port_map);
|
||||
}
|
||||
|
||||
/* Build unique X-direction connection block modules */
|
||||
for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) {
|
||||
const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANX, icb);
|
||||
|
||||
print_verilog_routing_connection_box_unique_module(module_manager,
|
||||
verilog_dir,
|
||||
subckt_dir,
|
||||
unique_mirror, CHANX,
|
||||
use_explicit_port_map);
|
||||
}
|
||||
|
||||
/* Build unique X-direction connection block modules */
|
||||
for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
|
||||
const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANY, icb);
|
||||
|
||||
print_verilog_routing_connection_box_unique_module(module_manager,
|
||||
verilog_dir,
|
||||
subckt_dir,
|
||||
unique_mirror, CHANY,
|
||||
use_explicit_port_map);
|
||||
}
|
||||
|
||||
vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n");
|
||||
dump_verilog_subckt_header_file(routing_verilog_subckt_file_path_head,
|
||||
subckt_dir.c_str(),
|
||||
routing_verilog_file_name);
|
||||
|
||||
}
|
||||
Loading…
Reference in New Issue