From 95c1fe61e1ae6ba53e46ad807fd19cd91f2f4543 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Jul 2020 13:49:03 -0600 Subject: [PATCH] use k6 n8 in mux design to speed up CI --- openfpga_flow/tasks/mux_design/local_encoder/config/task.conf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf b/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf index a9ddefc19..f34e31c44 100644 --- a/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf +++ b/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf @@ -15,12 +15,12 @@ spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif