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Merge pull request #864 from yunuseryilmaz18/master 

Update dpram16k.v, dpram_2048x8.v, and dpram1k.v
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tangxifan 2022-10-30 12:16:21 -07:00 committed by GitHub
parent 1445d5db0a 1abd6bca42
commit 958ef37a83
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 13 additions and 13 deletions
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4
openfpga_flow/openfpga_cell_library/verilog/dpram.v
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@ -14,7 +14,7 @@ module dpram (
input[0:31] d_in, input[0:31] d_in,
output[0:31] d_out ); output[0:31] d_out );
dual_port_sram memory_0 ( dpram_1024x32_core memory_0 (
.wclk (clk), .wclk (clk),
.wen (wen), .wen (wen),
.waddr (waddr), .waddr (waddr),
@ -26,7 +26,7 @@ module dpram (
endmodule endmodule
module dual_port_sram ( module dpram_1024x32_core (
input wclk, input wclk,
input wen, input wen,
input[0:9] waddr, input[0:9] waddr,

14
openfpga_flow/openfpga_cell_library/verilog/dpram16k.v
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@ -9,12 +9,12 @@ module dpram_512x32 (
input clk, input clk,
input wen, input wen,
input ren, input ren,
input[0:9] waddr, input[0:8] waddr,
input[0:9] raddr, input[0:8] raddr,
input[0:31] d_in, input[0:31] d_in,
output[0:31] d_out ); output[0:31] d_out );
dual_port_sram memory_0 ( dpram_512x32_core memory_0 (
.wclk (clk), .wclk (clk),
.wen (wen), .wen (wen),
.waddr (waddr), .waddr (waddr),
@ -26,17 +26,17 @@ module dpram_512x32 (
endmodule endmodule
module dual_port_sram ( module dpram_512x32_core (
input wclk, input wclk,
input wen, input wen,
input[0:9] waddr, input[0:8] waddr,
input[0:31] data_in, input[0:31] data_in,
input rclk, input rclk,
input ren, input ren,
input[0:9] raddr, input[0:8] raddr,
output[0:31] d_out ); output[0:31] d_out );
reg[0:31] ram[0:1023]; reg[0:31] ram[0:511];
reg[0:31] internal; reg[0:31] internal;
assign d_out = internal; assign d_out = internal;

4
openfpga_flow/openfpga_cell_library/verilog/dpram1k.v
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@ -14,7 +14,7 @@ module dpram_128x8 (
input[0:7] d_in, input[0:7] d_in,
output[0:7] d_out ); output[0:7] d_out );
dual_port_sram memory_0 ( dpram_128x8_core memory_0 (
.wclk (clk), .wclk (clk),
.wen (wen), .wen (wen),
.waddr (waddr), .waddr (waddr),
@ -26,7 +26,7 @@ module dpram_128x8 (
endmodule endmodule
module dual_port_sram ( module dpram_128x8_core (
input wclk, input wclk,
input wen, input wen,
input[0:6] waddr, input[0:6] waddr,

4
openfpga_flow/openfpga_cell_library/verilog/dpram_2048x8.v
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@ -14,7 +14,7 @@ module dpram_2048x8 (
input[0:7] data_in, input[0:7] data_in,
output[0:7] data_out ); output[0:7] data_out );
dual_port_sram memory_0 ( dpram_2048x8_core memory_0 (
.wclk (clk), .wclk (clk),
.wen (wen), .wen (wen),
.waddr (waddr), .waddr (waddr),
@ -32,7 +32,7 @@ endmodule
// Function : Core module of dual port RAM 2048 addresses x 8 bit // Function : Core module of dual port RAM 2048 addresses x 8 bit
// Coder : Xifan tang // Coder : Xifan tang
//----------------------------------------------------- //-----------------------------------------------------
module dual_port_sram ( module dpram_2048x8_core (
input wclk, input wclk,
input wen, input wen,
input[0:10] waddr, input[0:10] waddr,