From 9585e1d3b5f94e78a3802c8ed64675180fcd647f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 14 Jun 2021 14:00:34 -0600 Subject: [PATCH] [Doc] Update documentation about 'default_net_type' option in testbench generators --- .../openfpga_commands/fpga_verilog_commands.rst | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index 5c57d104e..2a9af3b96 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -76,6 +76,10 @@ write_full_testbench Use explicit port mapping when writing the Verilog netlists + .. option:: --default_net_type + + Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``. + .. option:: --include_signal_init Output signal initialization to Verilog testbench to smooth convergence in HDL simulation @@ -106,6 +110,10 @@ write_preconfigured_fabric_wrapper Use explicit port mapping when writing the Verilog netlists + .. option:: --default_net_type + + Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``. + .. option:: --support_icarus_simulator Output Verilog netlists with syntax that iVerilog simulator can accept @@ -140,6 +148,11 @@ write_preconfigured_testbench Use explicit port mapping when writing the Verilog netlists + .. option:: --default_net_type + + Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``. + + .. option:: --support_icarus_simulator Output Verilog netlists with syntax that iVerilog simulator can accept