[Tool] Trim dead codes in port naming function
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2c5634ee76
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@ -505,32 +505,14 @@ std::string generate_connection_block_module_name(const t_rr_type& cb_type,
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* This function will generate a full port name including coordinates
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* so that each pin in top-level netlists is unique!
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*********************************************************************/
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std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
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const size_t& width,
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std::string generate_grid_port_name(const size_t& width,
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const size_t& height,
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const int& subtile_index,
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const e_side& side,
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const BasicPort& pin_info,
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const bool& for_top_netlist) {
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const BasicPort& pin_info) {
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/* Ensure that the pin is 1-bit ONLY !!! */
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VTR_ASSERT(1 == pin_info.get_width());
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if (true == for_top_netlist) {
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std::string port_name = std::string("grid_");
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port_name += std::to_string(coordinate.x());
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port_name += std::string("__");
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port_name += std::to_string(coordinate.y());
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port_name += std::string("__pin_");
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port_name += std::to_string(height);
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port_name += std::string("__");
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port_name += std::to_string(size_t(side));
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port_name += std::string("__");
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port_name += pin_info.get_name();
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port_name += std::string("_");
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port_name += std::to_string(pin_info.get_lsb());
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port_name += std::string("_");
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return port_name;
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}
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/* For non-top netlist */
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VTR_ASSERT( false == for_top_netlist );
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SideManager side_manager(side);
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std::string port_name = std::string(side_manager.to_string());
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port_name += std::string("_width_");
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@ -559,8 +541,9 @@ std::string generate_grid_duplicated_port_name(const size_t& width,
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const e_side& side,
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const BasicPort& pin_info,
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const bool& upper_port) {
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/* Ensure that the pin is 1-bit ONLY !!! */
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VTR_ASSERT(1 == pin_info.get_width());
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/* For non-top netlist */
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SideManager side_manager(side);
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std::string port_name = std::string(side_manager.to_string());
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port_name += std::string("_width_");
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@ -585,12 +568,11 @@ std::string generate_grid_duplicated_port_name(const size_t& width,
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return port_name;
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}
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/*********************************************************************
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* Generate the port name for a grid in the context of a module
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* To keep a short and simple name, this function will not
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* include any grid coorindate information!
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*********************************************************************/
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**********************************************************************/
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std::string generate_grid_module_port_name(const size_t& pin_id) {
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/* For non-top netlist */
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std::string port_name = std::string("grid_");
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@ -135,13 +135,11 @@ std::string generate_pb_memory_instance_name(const std::string& prefix,
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t_pb_graph_pin* pb_graph_pin,
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const std::string& postfix);
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std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
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const size_t& width,
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std::string generate_grid_port_name(const size_t& width,
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const size_t& height,
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const int& subtile_index,
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const e_side& side,
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const BasicPort& pin_info,
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const bool& for_top_netlist);
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const BasicPort& pin_info);
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std::string generate_grid_duplicated_port_name(const size_t& width,
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const size_t& height,
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@ -100,8 +100,7 @@ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager,
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/* Xifan: I assume that each direct connection pin must have Fc=0. */
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|| ( (DRIVER == pin_class_type)
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&& (0. == find_physical_tile_pin_Fc(grid_type_descriptor, ipin)) ) ) {
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vtr::Point<size_t> dummy_coordinate;
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std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, subtile_index, side, pin_info, false);
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std::string port_name = generate_grid_port_name(iwidth, iheight, subtile_index, side, pin_info);
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BasicPort grid_port(port_name, 0, 0);
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/* Add the port to the module */
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module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]);
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@ -188,8 +187,7 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m
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/* Create a net to connect the grid pin to child module pin */
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ModuleNetId net = module_manager.create_module_net(grid_module);
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/* Find the port in grid_module */
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vtr::Point<size_t> dummy_coordinate;
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std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_width, pin_height, subtile_index, side, pin_info, false);
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std::string grid_port_name = generate_grid_port_name(pin_width, pin_height, subtile_index, side, pin_info);
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ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id));
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@ -79,12 +79,11 @@ void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager,
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/* Create a net to connect the grid pin to child module pin */
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ModuleNetId net = module_manager.create_module_net(grid_module);
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/* Find the port in grid_module */
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vtr::Point<size_t> dummy_coordinate;
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BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, grid_pin_index);
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VTR_ASSERT(true == pin_info.is_valid());
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int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, grid_pin_index);
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VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity);
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std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_width, pin_height, subtile_index, side, pin_info, false);
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std::string grid_port_name = generate_grid_port_name(pin_width, pin_height, subtile_index, side, pin_info);
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ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id));
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/* Grid port always has only 1 pin, it is assumed when adding these ports to the module
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@ -77,12 +77,11 @@ void add_grid_module_pb_type_ports(ModuleManager& module_manager,
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/* Generate the pin name,
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* we give a empty coordinate but it will not be used (see details in the function
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*/
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vtr::Point<size_t> dummy_coordinate;
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BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, ipin);
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VTR_ASSERT(true == pin_info.is_valid());
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int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, ipin);
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VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity);
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std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, subtile_index, side, pin_info, false);
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std::string port_name = generate_grid_port_name(iwidth, iheight, subtile_index, side, pin_info);
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BasicPort grid_port(port_name, 0, 0);
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/* Add the port to the module */
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module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]);
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@ -121,9 +121,9 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager,
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VTR_ASSERT(true == src_grid_pin_info.is_valid());
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int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, src_grid_pin_index);
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VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity);
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std::string src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_width, src_grid_pin_height, subtile_index,
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std::string src_grid_port_name = generate_grid_port_name(src_grid_pin_width, src_grid_pin_height, subtile_index,
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rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
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src_grid_pin_info, false);
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src_grid_pin_info);
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ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id));
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BasicPort src_grid_port = module_manager.module_port(src_grid_module, src_grid_port_id);
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@ -267,9 +267,9 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager
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*/
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std::string src_grid_port_name;
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if (0. == find_physical_tile_pin_Fc(grid_type_descriptor, src_grid_pin_index)) {
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src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_width, src_grid_pin_height, subtile_index,
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src_grid_port_name = generate_grid_port_name(src_grid_pin_width, src_grid_pin_height, subtile_index,
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rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
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src_grid_pin_info, false);
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src_grid_pin_info);
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} else {
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src_grid_port_name = generate_grid_duplicated_port_name(src_grid_pin_width, src_grid_pin_height, subtile_index,
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rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
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@ -438,9 +438,9 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager,
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VTR_ASSERT(true == sink_grid_pin_info.is_valid());
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int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, sink_grid_pin_index);
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VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity);
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std::string sink_grid_port_name = generate_grid_port_name(grid_coordinate, sink_grid_pin_width, sink_grid_pin_height, subtile_index,
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std::string sink_grid_port_name = generate_grid_port_name(sink_grid_pin_width, sink_grid_pin_height, subtile_index,
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rr_graph.node_side(rr_gsb.get_ipin_node(cb_ipin_side, inode)),
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sink_grid_pin_info, false);
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sink_grid_pin_info);
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ModulePortId sink_grid_port_id = module_manager.find_module_port(sink_grid_module, sink_grid_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_grid_port_id));
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BasicPort sink_grid_port = module_manager.module_port(sink_grid_module, sink_grid_port_id);
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@ -792,10 +792,9 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana
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/* Build nets */
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for (const e_side& pin_side : pin_sides) {
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std::string grid_port_name = generate_grid_port_name(grid_coordinate,
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grid_pin_width, grid_pin_height, subtile_index,
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std::string grid_port_name = generate_grid_port_name(grid_pin_width, grid_pin_height, subtile_index,
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pin_side,
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grid_pin_info, false);
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grid_pin_info);
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ModulePortId grid_port_id = module_manager.find_module_port(grid_module, grid_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_port_id));
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@ -102,7 +102,7 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager,
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VTR_ASSERT(true == src_pin_info.is_valid());
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int src_subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(src_grid_type_descriptor, src_tile_pin);
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VTR_ASSERT(OPEN != src_subtile_index && src_subtile_index < src_grid_type_descriptor->capacity);
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std::string src_port_name = generate_grid_port_name(src_clb_coord, src_pin_width, src_pin_height, src_subtile_index, src_pin_grid_side, src_pin_info, false);
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std::string src_port_name = generate_grid_port_name(src_pin_width, src_pin_height, src_subtile_index, src_pin_grid_side, src_pin_info);
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ModulePortId src_port_id = module_manager.find_module_port(src_grid_module, src_port_name);
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if (true != module_manager.valid_module_port_id(src_grid_module, src_port_id)) {
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VTR_LOG_ERROR("Fail to find port '%s[%lu][%lu].%s'\n",
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@ -124,7 +124,7 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager,
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VTR_ASSERT(true == sink_pin_info.is_valid());
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int sink_subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(sink_grid_type_descriptor, sink_tile_pin);
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VTR_ASSERT(OPEN != src_subtile_index && src_subtile_index < sink_grid_type_descriptor->capacity);
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std::string sink_port_name = generate_grid_port_name(des_clb_coord, sink_pin_width, sink_pin_height, sink_subtile_index, sink_pin_grid_side, sink_pin_info, false);
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std::string sink_port_name = generate_grid_port_name(sink_pin_width, sink_pin_height, sink_subtile_index, sink_pin_grid_side, sink_pin_info);
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ModulePortId sink_port_id = module_manager.find_module_port(sink_grid_module, sink_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_port_id));
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VTR_ASSERT(1 == module_manager.module_port(sink_grid_module, sink_port_id).get_width());
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