[Tool] Trim dead codes in port naming function

openfpga/src/base/openfpga_naming.cpp

@@ -505,32 +505,14 @@ std::string generate_connection_block_module_name(const t_rr_type& cb_type,
  * This function will generate a full port name including coordinates
  * so that each pin in top-level netlists is unique!
  *********************************************************************/
-std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
+std::string generate_grid_port_name(const size_t& width, 
-                                    const size_t& width, 
                                     const size_t& height, 
                                     const int& subtile_index, 
                                     const e_side& side, 
-                                    const BasicPort& pin_info,
+                                    const BasicPort& pin_info) {
-                                    const bool& for_top_netlist) {
+  /* Ensure that the pin is 1-bit ONLY !!! */
   VTR_ASSERT(1 == pin_info.get_width());
-  if (true == for_top_netlist) {
+
-    std::string port_name = std::string("grid_");
-    port_name += std::to_string(coordinate.x());
-    port_name += std::string("__");
-    port_name += std::to_string(coordinate.y());
-    port_name += std::string("__pin_");
-    port_name += std::to_string(height);
-    port_name += std::string("__");
-    port_name += std::to_string(size_t(side));
-    port_name += std::string("__");
-    port_name += pin_info.get_name();
-    port_name += std::string("_");
-    port_name += std::to_string(pin_info.get_lsb());
-    port_name += std::string("_");
-    return port_name;
-  } 
-  /* For non-top netlist */
-  VTR_ASSERT( false == for_top_netlist );
   SideManager side_manager(side);
   std::string port_name = std::string(side_manager.to_string());
   port_name += std::string("_width_");
@@ -559,8 +541,9 @@ std::string generate_grid_duplicated_port_name(const size_t& width,
                                                const e_side& side, 
                                                const BasicPort& pin_info,
                                                const bool& upper_port) {
+  /* Ensure that the pin is 1-bit ONLY !!! */
   VTR_ASSERT(1 == pin_info.get_width());
-  /* For non-top netlist */
+
   SideManager side_manager(side);
   std::string port_name = std::string(side_manager.to_string());
   port_name += std::string("_width_");
@@ -585,12 +568,11 @@ std::string generate_grid_duplicated_port_name(const size_t& width,
   return port_name;
 }
 
-
 /*********************************************************************
  * Generate the port name for a grid in the context of a module
  * To keep a short and simple name, this function will not 
  * include any grid coorindate information!
- *********************************************************************/
+ **********************************************************************/
 std::string generate_grid_module_port_name(const size_t& pin_id) {
   /* For non-top netlist */
   std::string port_name = std::string("grid_");

openfpga/src/base/openfpga_naming.h

@@ -135,13 +135,11 @@ std::string generate_pb_memory_instance_name(const std::string& prefix,
                                              t_pb_graph_pin* pb_graph_pin, 
                                              const std::string& postfix);
 
-std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
+std::string generate_grid_port_name(const size_t& width, 
-                                    const size_t& width, 
                                     const size_t& height, 
                                     const int& subtile_index, 
                                     const e_side& side, 
-                                    const BasicPort& pin_info,
+                                    const BasicPort& pin_info);
-                                    const bool& for_top_netlist);
 
 std::string generate_grid_duplicated_port_name(const size_t& width,
                                                const size_t& height, 

openfpga/src/fabric/build_grid_module_duplicated_pins.cpp

@@ -100,8 +100,7 @@ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager,
             /* Xifan: I assume that each direct connection pin must have Fc=0. */
             || ( (DRIVER == pin_class_type)
               && (0. == find_physical_tile_pin_Fc(grid_type_descriptor, ipin)) ) ) {
-            vtr::Point<size_t> dummy_coordinate;
+            std::string port_name = generate_grid_port_name(iwidth, iheight, subtile_index, side, pin_info);
-            std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, subtile_index, side, pin_info, false);
             BasicPort grid_port(port_name, 0, 0);
             /* Add the port to the module */
             module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]);
@@ -188,8 +187,7 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m
       /* Create a net to connect the grid pin to child module pin */
       ModuleNetId net = module_manager.create_module_net(grid_module);
       /* Find the port in grid_module */
-      vtr::Point<size_t> dummy_coordinate;
+      std::string grid_port_name = generate_grid_port_name(pin_width, pin_height, subtile_index, side, pin_info);
-      std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_width, pin_height, subtile_index, side, pin_info, false);
       ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name);
       VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id));
 

openfpga/src/fabric/build_grid_module_utils.cpp

@@ -79,12 +79,11 @@ void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager,
     /* Create a net to connect the grid pin to child module pin */
     ModuleNetId net = module_manager.create_module_net(grid_module);
     /* Find the port in grid_module */
-    vtr::Point<size_t> dummy_coordinate;
     BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, grid_pin_index);
     VTR_ASSERT(true == pin_info.is_valid());
     int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, grid_pin_index);
     VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity);
-    std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_width, pin_height, subtile_index, side, pin_info, false);
+    std::string grid_port_name = generate_grid_port_name(pin_width, pin_height, subtile_index, side, pin_info);
     ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name);
     VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id));
     /* Grid port always has only 1 pin, it is assumed when adding these ports to the module

openfpga/src/fabric/build_grid_modules.cpp

@@ -77,12 +77,11 @@ void add_grid_module_pb_type_ports(ModuleManager& module_manager,
           /* Generate the pin name, 
            * we give a empty coordinate but it will not be used (see details in the function 
            */
-          vtr::Point<size_t> dummy_coordinate;
           BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, ipin);
           VTR_ASSERT(true == pin_info.is_valid());
           int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, ipin);
           VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity);
-          std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, subtile_index, side, pin_info, false);
+          std::string port_name = generate_grid_port_name(iwidth, iheight, subtile_index, side, pin_info);
           BasicPort grid_port(port_name, 0, 0);
           /* Add the port to the module */
           module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]);

openfpga/src/fabric/build_top_module_connection.cpp

@@ -121,9 +121,9 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager,
       VTR_ASSERT(true == src_grid_pin_info.is_valid());
       int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, src_grid_pin_index);
       VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity);
-      std::string src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_width, src_grid_pin_height, subtile_index,
+      std::string src_grid_port_name = generate_grid_port_name(src_grid_pin_width, src_grid_pin_height, subtile_index,
                                                                rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
-                                                               src_grid_pin_info, false);
+                                                               src_grid_pin_info);
       ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name);
       VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id));
       BasicPort src_grid_port = module_manager.module_port(src_grid_module, src_grid_port_id); 
@@ -267,9 +267,9 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager
        */
       std::string src_grid_port_name;
       if (0. == find_physical_tile_pin_Fc(grid_type_descriptor, src_grid_pin_index)) {
-        src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_width, src_grid_pin_height, subtile_index,
+        src_grid_port_name = generate_grid_port_name(src_grid_pin_width, src_grid_pin_height, subtile_index,
                                                      rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
-                                                     src_grid_pin_info, false);
+                                                     src_grid_pin_info);
       } else {
        src_grid_port_name = generate_grid_duplicated_port_name(src_grid_pin_width, src_grid_pin_height, subtile_index, 
                                                                rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
@@ -438,9 +438,9 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager,
       VTR_ASSERT(true == sink_grid_pin_info.is_valid());
       int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, sink_grid_pin_index);
       VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity);
-      std::string sink_grid_port_name = generate_grid_port_name(grid_coordinate, sink_grid_pin_width, sink_grid_pin_height, subtile_index,
+      std::string sink_grid_port_name = generate_grid_port_name(sink_grid_pin_width, sink_grid_pin_height, subtile_index,
                                                                 rr_graph.node_side(rr_gsb.get_ipin_node(cb_ipin_side, inode)),
-                                                                sink_grid_pin_info, false);
+                                                                sink_grid_pin_info);
       ModulePortId sink_grid_port_id = module_manager.find_module_port(sink_grid_module, sink_grid_port_name);
       VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_grid_port_id));
       BasicPort sink_grid_port = module_manager.module_port(sink_grid_module, sink_grid_port_id); 
@@ -792,10 +792,9 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana
 
       /* Build nets */
       for (const e_side& pin_side : pin_sides) {
-        std::string grid_port_name = generate_grid_port_name(grid_coordinate,
+        std::string grid_port_name = generate_grid_port_name(grid_pin_width, grid_pin_height, subtile_index,
-                                                             grid_pin_width, grid_pin_height, subtile_index,
                                                              pin_side,
-                                                             grid_pin_info, false);
+                                                             grid_pin_info);
         ModulePortId grid_port_id = module_manager.find_module_port(grid_module, grid_port_name);
         VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_port_id));
 

openfpga/src/fabric/build_top_module_directs.cpp

@@ -102,7 +102,7 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager,
   VTR_ASSERT(true == src_pin_info.is_valid());
   int src_subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(src_grid_type_descriptor, src_tile_pin);
   VTR_ASSERT(OPEN != src_subtile_index && src_subtile_index < src_grid_type_descriptor->capacity);
-  std::string src_port_name = generate_grid_port_name(src_clb_coord, src_pin_width, src_pin_height, src_subtile_index, src_pin_grid_side, src_pin_info, false);
+  std::string src_port_name = generate_grid_port_name(src_pin_width, src_pin_height, src_subtile_index, src_pin_grid_side, src_pin_info);
   ModulePortId src_port_id = module_manager.find_module_port(src_grid_module, src_port_name); 
   if (true != module_manager.valid_module_port_id(src_grid_module, src_port_id)) {
     VTR_LOG_ERROR("Fail to find port '%s[%lu][%lu].%s'\n",
@@ -124,7 +124,7 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager,
   VTR_ASSERT(true == sink_pin_info.is_valid());
   int sink_subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(sink_grid_type_descriptor, sink_tile_pin);
   VTR_ASSERT(OPEN != src_subtile_index && src_subtile_index < sink_grid_type_descriptor->capacity);
-  std::string sink_port_name = generate_grid_port_name(des_clb_coord, sink_pin_width, sink_pin_height, sink_subtile_index, sink_pin_grid_side, sink_pin_info, false);
+  std::string sink_port_name = generate_grid_port_name(sink_pin_width, sink_pin_height, sink_subtile_index, sink_pin_grid_side, sink_pin_info);
   ModulePortId sink_port_id = module_manager.find_module_port(sink_grid_module, sink_port_name); 
   VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_port_id));
   VTR_ASSERT(1 == module_manager.module_port(sink_grid_module, sink_port_id).get_width());