From 95674c4687e650d1485736e15b61993c670488b1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Jul 2019 10:00:02 -0600 Subject: [PATCH] added Switch Block SubType and SubFs for tileable rr_graph generation --- .../libarchfpga/SRC/include/physical_types.h | 2 + vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c | 65 +++++++++++++++- vpr7_x2p/vpr/SRC/base/SetupVPR.c | 2 + vpr7_x2p/vpr/SRC/base/place_and_route.c | 6 +- vpr7_x2p/vpr/SRC/base/vpr_types.h | 2 + .../rr_graph/tileable_rr_graph_builder.cpp | 10 ++- .../rr_graph/tileable_rr_graph_builder.h | 1 + .../device/rr_graph/tileable_rr_graph_gsb.cpp | 4 +- .../device/rr_graph/tileable_rr_graph_gsb.h | 2 + .../fpga_x2p/base/fpga_x2p_bitstream_utils.c | 75 ++++++++++++++----- .../fpga_x2p/base/fpga_x2p_bitstream_utils.h | 3 + .../bitstream/fpga_bitstream_pbtypes.c | 2 + .../vpr/SRC/fpga_x2p/router/fpga_x2p_router.c | 49 +++++++++++- .../vpr/SRC/fpga_x2p/spice/spice_routing.c | 4 +- vpr7_x2p/vpr/SRC/place/timing_place_lookup.c | 6 +- vpr7_x2p/vpr/SRC/route/route_common.c | 6 +- vpr7_x2p/vpr/SRC/route/rr_graph.c | 7 +- vpr7_x2p/vpr/SRC/route/rr_graph.h | 1 + 18 files changed, 209 insertions(+), 38 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/include/physical_types.h b/vpr7_x2p/libarchfpga/SRC/include/physical_types.h index bdc991718..6e7a064e7 100644 --- a/vpr7_x2p/libarchfpga/SRC/include/physical_types.h +++ b/vpr7_x2p/libarchfpga/SRC/include/physical_types.h @@ -931,9 +931,11 @@ struct s_arch { bool tileable; /* Xifan TANG: tileable rr_graph support */ t_chan_width_dist Chans; enum e_switch_block_type SBType; + enum e_switch_block_type SBSubType; float R_minW_nmos; float R_minW_pmos; int Fs; + int SubFs; float C_ipin_cblock; float T_ipin_cblock; /* mrFPGA: Xifan TANG */ diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c b/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c index ff8ececa1..e93a05914 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c @@ -1,4 +1,39 @@ -/* The XML parser processes an XML file into a tree data structure composed of * +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: rr_blocks.cpp + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/07/02 | Xifan Tang | Modified to support passing_track_type for switch blocks + * +-------------------------------------+ + ***********************************************************************/ +/************************************************************************ + * The XML parser processes an XML file into a tree data structure composed of * * ezxml_t nodes. Each ezxml_t node represents an XML element. For example * * will generate two ezxml_t nodes. One called "a" and its * * child "b". Each ezxml_t node can contain various XML data such as attribute * @@ -22,7 +57,7 @@ * Because of how the XML tree traversal works, we free everything when we're * * done reading an architecture file to make sure that there isn't some part * * of the architecture file that got missed. * - */ + ***********************************************************************/ #include #include @@ -2142,6 +2177,29 @@ static void ProcessDevice(INOUTP ezxml_t Node, OUTP struct s_arch *arch, arch->Fs = GetIntProperty(Cur, "fs", TRUE, 3); + /* SubType is the switch block type of passing tracks */ + /* By default, the subType is the same as the main type */ + Prop = FindProperty(Cur, "sub_type", FALSE); + if (NULL != Prop) { + if (strcmp(Prop, "wilton") == 0) { + arch->SBSubType = WILTON; + } else if (strcmp(Prop, "universal") == 0) { + arch->SBSubType = UNIVERSAL; + } else if (strcmp(Prop, "subset") == 0) { + arch->SBSubType = SUBSET; + } else { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] Unknown property %s for switch block type x\n", + Cur->line, Prop); + exit(1); + } + } + ezxml_set_attr(Cur, "sub_type", NULL); + + /* SubFs is Fs for the switch block type of passing tracks */ + /* By default, the subFs is the same as the main Fs */ + arch->SubFs = GetIntProperty(Cur, "sub_fs", FALSE, arch->Fs); + FreeNode(Cur); } @@ -4132,3 +4190,6 @@ void SetupPinEquivalenceAutoDetect(ezxml_t Parent, t_type_descriptor* Type) { return; } +/************************************************************************ + * End of file : read_xml_arch_file.c + ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/base/SetupVPR.c b/vpr7_x2p/vpr/SRC/base/SetupVPR.c index 09441daa1..af240a0ea 100644 --- a/vpr7_x2p/vpr/SRC/base/SetupVPR.c +++ b/vpr7_x2p/vpr/SRC/base/SetupVPR.c @@ -536,9 +536,11 @@ static void SetupRoutingArch(INP t_arch Arch, OUTP struct s_det_routing_arch *RoutingArch) { RoutingArch->switch_block_type = Arch.SBType; + RoutingArch->switch_block_sub_type = Arch.SBSubType; RoutingArch->R_minW_nmos = Arch.R_minW_nmos; RoutingArch->R_minW_pmos = Arch.R_minW_pmos; RoutingArch->Fs = Arch.Fs; + RoutingArch->sub_Fs = Arch.SubFs; RoutingArch->directionality = BI_DIRECTIONAL; if (Arch.Segments) RoutingArch->directionality = Arch.Segments[0].directionality; diff --git a/vpr7_x2p/vpr/SRC/base/place_and_route.c b/vpr7_x2p/vpr/SRC/base/place_and_route.c index e314e0882..f4c53e72b 100644 --- a/vpr7_x2p/vpr/SRC/base/place_and_route.c +++ b/vpr7_x2p/vpr/SRC/base/place_and_route.c @@ -560,8 +560,10 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts, free_rr_graph(); build_rr_graph(graph_type, num_types, type_descriptors, nx, ny, grid, - chan_width_x[0], NULL, det_routing_arch.switch_block_type, - det_routing_arch.Fs, det_routing_arch.num_segment, + chan_width_x[0], NULL, + det_routing_arch.switch_block_type, det_routing_arch.Fs, + det_routing_arch.switch_block_sub_type, det_routing_arch.sub_Fs, + det_routing_arch.num_segment, det_routing_arch.num_switch, segment_inf, det_routing_arch.global_route_switch, det_routing_arch.delayless_switch, timing_inf, diff --git a/vpr7_x2p/vpr/SRC/base/vpr_types.h b/vpr7_x2p/vpr/SRC/base/vpr_types.h index 02a0d3657..cd163d111 100755 --- a/vpr7_x2p/vpr/SRC/base/vpr_types.h +++ b/vpr7_x2p/vpr/SRC/base/vpr_types.h @@ -807,6 +807,8 @@ struct s_det_routing_arch { enum e_directionality directionality; /* UDSD by AY */ int Fs; enum e_switch_block_type switch_block_type; + int sub_Fs; + enum e_switch_block_type switch_block_sub_type; int num_segment; short num_switch; short global_route_switch; diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp index 697a10166..2e56e693f 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp @@ -31,6 +31,8 @@ * +-------------------------------------+ * | 2019/06/11 | Xifan Tang | Created * +-------------------------------------+ + * | 2019/07/02 | Xifan Tang | Modified to support SB subtype and SubFs + * +-------------------------------------+ ***********************************************************************/ /************************************************************************ * This file contains a builder for the complex rr_graph data structure @@ -777,7 +779,8 @@ void build_rr_graph_edges(t_rr_graph* rr_graph, const std::vector device_chan_width, const std::vector segment_inf, int** Fc_in, int** Fc_out, - const enum e_switch_block_type sb_type, const int Fs) { + const enum e_switch_block_type sb_type, const int Fs, + const enum e_switch_block_type sb_subtype, const int subFs) { /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ build_rr_graph_edges_for_source_nodes(rr_graph, grids); @@ -804,7 +807,7 @@ void build_rr_graph_edges(t_rr_graph* rr_graph, /* adapt the switch_block_conn for the GSB nodes */ t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ - sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, sb_type, Fs, segment_inf); + sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, sb_type, Fs, sb_subtype, subFs, segment_inf); /* Build edges for a GSB */ build_edges_for_one_tileable_rr_gsb(rr_graph, &rr_gsb, @@ -904,6 +907,7 @@ void build_tileable_unidir_rr_graph(INP const int L_num_types, INP t_type_ptr types, INP const int L_nx, INP const int L_ny, INP struct s_grid_tile **L_grid, INP const int chan_width, INP const enum e_switch_block_type sb_type, INP const int Fs, + INP const enum e_switch_block_type sb_subtype, INP const int subFs, INP const int num_seg_types, INP const t_segment_inf * segment_inf, INP const int num_switches, INP const int delayless_switch, @@ -1021,7 +1025,7 @@ void build_tileable_unidir_rr_graph(INP const int L_num_types, /* Create edges for a tileable rr_graph */ build_rr_graph_edges(&rr_graph, device_size, grids, device_chan_width, segment_infs, Fc_in, Fc_out, - sb_type, Fs); + sb_type, Fs, sb_subtype, subFs); /************************************************************************ * 6.2 Build direction connection lists diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h index 827adbbc8..5844a55d5 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h @@ -9,6 +9,7 @@ void build_tileable_unidir_rr_graph(INP const int L_num_types, INP t_type_ptr types, INP const int L_nx, INP const int L_ny, INP struct s_grid_tile **L_grid, INP const int chan_width, INP const enum e_switch_block_type sb_type, INP const int Fs, + INP const enum e_switch_block_type sb_subtype, INP const int subFs, INP const int num_seg_types, INP const t_segment_inf * segment_inf, INP const int num_switches, INP const int delayless_switch, diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp index d0eaa901f..27f111091 100755 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp @@ -475,6 +475,8 @@ t_track2track_map build_gsb_track_to_track_map(const t_rr_graph* rr_graph, const RRGSB& rr_gsb, const enum e_switch_block_type sb_type, const int Fs, + const enum e_switch_block_type sb_subtype, + const int subFs, const std::vector segment_inf) { t_track2track_map track2track_map; /* [0..gsb_side][0..chan_width][track_indices] */ @@ -555,7 +557,7 @@ t_track2track_map build_gsb_track_to_track_map(const t_rr_graph* rr_graph, * TODO: This can be improved with different patterns! */ build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, - sb_type, Fs, + sb_subtype, subFs, pass_tracks, start_tracks, &track2track_map); diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.h b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.h index 6d98e1aa8..5f5a4cb49 100755 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.h +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.h @@ -23,6 +23,8 @@ t_track2track_map build_gsb_track_to_track_map(const t_rr_graph* rr_graph, const RRGSB& rr_gsb, const enum e_switch_block_type sb_type, const int Fs, + const enum e_switch_block_type sb_subtype, + const int subFs, const std::vector segment_inf); RRGSB build_one_tileable_rr_gsb(const DeviceCoordinator& device_range, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c index fde3b52c7..a300ded24 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c @@ -1,3 +1,41 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: fpga_x2p_bitstream_utils.c + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/07/02 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ +/************************************************************************ + * This file contains most utilized functions for the bitstream generator + ***********************************************************************/ + /***********************************/ /* Synthesizable Verilog Dumping */ /* Xifan TANG, EPFL/LSI */ @@ -30,11 +68,14 @@ #include "fpga_x2p_mux_utils.h" #include "fpga_x2p_globals.h" +#include "fpga_x2p_bitstream_utils.h" + /* Determine the size of input address of a decoder */ int determine_decoder_size(int num_addr_out) { return ceil(log(num_addr_out)/log(2.)); } +static int count_num_sram_bits_one_lut_spice_model(t_spice_model* cur_spice_model) { int num_sram_bits = 0; int iport; @@ -98,6 +139,7 @@ int count_num_sram_bits_one_lut_spice_model(t_spice_model* cur_spice_model) { return num_sram_bits; } +static int count_num_sram_bits_one_mux_spice_model(t_spice_model* cur_spice_model, int mux_size) { int num_sram_bits = 0; @@ -162,7 +204,7 @@ int count_num_sram_bits_one_mux_spice_model(t_spice_model* cur_spice_model, return num_sram_bits; } - +static int count_num_sram_bits_one_generic_spice_model(t_spice_model* cur_spice_model) { int iport; int num_sram_bits = 0; @@ -227,6 +269,7 @@ int count_num_sram_bits_one_spice_model(t_spice_model* cur_spice_model, return -1; } +static int count_num_mode_bits_one_generic_spice_model(t_spice_model* cur_spice_model) { int iport; int num_mode_bits = 0; @@ -424,20 +467,7 @@ int count_num_reserved_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_mo break; case SPICE_SRAM_SCAN_CHAIN: case SPICE_SRAM_STANDALONE: - /* 4T1R MUX requires more configuration bits */ - if (SPICE_MODEL_STRUCTURE_TREE == cur_spice_model->design_tech_info.mux_info->structure) { - /* For tree-structure: we need 3 times more config. bits */ - num_reserved_conf_bits = 0; - } else if (SPICE_MODEL_STRUCTURE_MULTILEVEL == cur_spice_model->design_tech_info.mux_info->structure) { - /* For multi-level structure: we need 1 more config. bits for each level */ - num_reserved_conf_bits = 0; - } else { - num_reserved_conf_bits = 0; - } - /* For 2:1 MUX, whatever structure, there is only one level */ - if (2 == num_input_size) { - num_reserved_conf_bits = 0; - } + num_reserved_conf_bits = 0; break; default: vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", @@ -533,7 +563,7 @@ int count_num_reserved_conf_bits_one_spice_model(t_spice_model* cur_spice_model, return num_reserved_conf_bits; } - +static int count_num_conf_bits_one_lut_spice_model(t_spice_model* cur_spice_model, enum e_sram_orgz cur_sram_orgz_type) { int num_conf_bits = 0; @@ -611,7 +641,7 @@ int count_num_conf_bits_one_lut_spice_model(t_spice_model* cur_spice_model, return num_conf_bits; } - +static int count_num_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_model, enum e_sram_orgz cur_sram_orgz_type, int mux_size) { @@ -684,6 +714,7 @@ int count_num_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_model, return num_conf_bits; } +static int count_num_conf_bits_one_generic_spice_model(t_spice_model* cur_spice_model, enum e_sram_orgz cur_sram_orgz_type) { int num_conf_bits = 0; @@ -1098,9 +1129,9 @@ add_mux_conf_bits_to_llist(int mux_size, } /* Add SCFF configutration bits to a linked list*/ -void -add_sram_scff_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, - int num_sram_bits, int* sram_bits) { +static +void add_sram_scff_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, + int num_sram_bits, int* sram_bits) { int ibit, cur_mem_bit; t_conf_bit** sram_bit = NULL; t_spice_model* cur_sram_spice_model = NULL; @@ -1592,3 +1623,7 @@ void add_mux_conf_bits_to_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, return; } + +/************************************************************************ + * End of file : fpga_x2p_bitstream_utils.c + ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h index a63af4565..6f8c7751d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h @@ -24,6 +24,9 @@ int count_num_reserved_conf_bits_one_spice_model(t_spice_model* cur_spice_model, enum e_sram_orgz cur_sram_orgz_type, int mux_size); +int count_num_reserved_conf_bit_one_interc(t_interconnect* cur_interc, + enum e_sram_orgz cur_sram_orgz_type); + void add_mux_scff_conf_bits_to_llist(int mux_size, t_sram_orgz_info* cur_sram_orgz_info, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_pbtypes.c index c752765a5..4741521fe 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_pbtypes.c @@ -30,6 +30,8 @@ #include "fpga_x2p_bitstream_utils.h" #include "fpga_bitstream_primitives.h" +#include "fpga_bitstream_pbtypes.h" + /***** Subroutines *****/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_router.c b/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_router.c index e2585a215..c6de5ced7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_router.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_router.c @@ -1,3 +1,41 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: fpga_x2p_router.c + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/07/02 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ +/************************************************************************ + * This file contains a breadth-first router which is tailored for packer + ***********************************************************************/ + #include #include #include @@ -14,6 +52,8 @@ #include "fpga_x2p_rr_graph_utils.h" #include "fpga_x2p_pb_rr_graph.h" +#include "fpga_x2p_router.h" + void breadth_first_expand_rr_graph_trace_segment(t_rr_graph* local_rr_graph, t_trace *start_ptr, int remaining_connections_to_sink) { @@ -145,6 +185,7 @@ void breadth_first_add_source_to_rr_graph_heap(t_rr_graph* local_rr_graph, /* A copy of breath_first_add_source_to_heap_cluster * I remove all the use of global variables */ +static void breadth_first_add_one_source_to_rr_graph_heap(t_rr_graph* local_rr_graph, int src_net_index, int src_idx) { @@ -249,6 +290,7 @@ boolean breadth_first_route_one_net_pb_rr_graph(t_rr_graph* local_rr_graph, /* Adapt for the multi-source rr_graph routing */ +static boolean breadth_first_route_one_single_source_net_pb_rr_graph(t_rr_graph* local_rr_graph, int inet, int isrc, int start_isink, @@ -434,6 +476,7 @@ boolean breadth_first_route_one_single_source_net_pb_rr_graph(t_rr_graph* local_ /* Adapt for the multi-source rr_graph routing */ +static boolean breadth_first_route_one_multi_source_net_pb_rr_graph(t_rr_graph* local_rr_graph, int inet) { @@ -550,7 +593,7 @@ boolean breadth_first_route_one_multi_source_net_pb_rr_graph(t_rr_graph* local_r return route_success; } - +static boolean feasible_routing_rr_graph(t_rr_graph* local_rr_graph, boolean verbose) { @@ -845,5 +888,7 @@ boolean try_breadth_first_route_pb_rr_graph(t_rr_graph* local_rr_graph) { return (FALSE); } - +/************************************************************************ + * End of file : fpga_x2p_router.c + ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c index 78c0f18d4..73353e59d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c @@ -23,7 +23,7 @@ ***********************************************************************/ /************************************************************************ - * Filename: rr_blocks.cpp + * Filename: spice_routing.c * Created by: Xifan Tang * Change history: * +-------------------------------------+ @@ -1309,5 +1309,5 @@ void generate_spice_routing_resources(char* subckt_dir, } /************************************************************************ - * End of file : rr_blocks.cpp + * End of file : spice_routing.c ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/place/timing_place_lookup.c b/vpr7_x2p/vpr/SRC/place/timing_place_lookup.c index 88a4e7a29..b0d6bdbc9 100755 --- a/vpr7_x2p/vpr/SRC/place/timing_place_lookup.c +++ b/vpr7_x2p/vpr/SRC/place/timing_place_lookup.c @@ -459,8 +459,10 @@ static void alloc_routing_structs(struct s_router_opts router_opts, } build_rr_graph(graph_type, num_types, dummy_type_descriptors, nx, ny, grid, - chan_width_x[0], NULL, det_routing_arch.switch_block_type, - det_routing_arch.Fs, det_routing_arch.num_segment, + chan_width_x[0], NULL, + det_routing_arch.switch_block_type, det_routing_arch.Fs, + det_routing_arch.switch_block_sub_type, det_routing_arch.sub_Fs, + det_routing_arch.num_segment, det_routing_arch.num_switch, segment_inf, det_routing_arch.global_route_switch, det_routing_arch.delayless_switch, timing_inf, diff --git a/vpr7_x2p/vpr/SRC/route/route_common.c b/vpr7_x2p/vpr/SRC/route/route_common.c index 165b54f4a..58cbfca31 100755 --- a/vpr7_x2p/vpr/SRC/route/route_common.c +++ b/vpr7_x2p/vpr/SRC/route/route_common.c @@ -297,8 +297,10 @@ boolean try_route(int width_fac, struct s_router_opts router_opts, /* Set up the routing resource graph defined by this FPGA architecture. */ build_rr_graph(graph_type, num_types, type_descriptors, nx, ny, grid, - chan_width_x[0], NULL, det_routing_arch.switch_block_type, - det_routing_arch.Fs, det_routing_arch.num_segment, + chan_width_x[0], NULL, + det_routing_arch.switch_block_type, det_routing_arch.Fs, + det_routing_arch.switch_block_sub_type, det_routing_arch.sub_Fs, + det_routing_arch.num_segment, det_routing_arch.num_switch, segment_inf, det_routing_arch.global_route_switch, det_routing_arch.delayless_switch, timing_inf, diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph.c b/vpr7_x2p/vpr/SRC/route/rr_graph.c index ff6d76b3f..afe937e9a 100755 --- a/vpr7_x2p/vpr/SRC/route/rr_graph.c +++ b/vpr7_x2p/vpr/SRC/route/rr_graph.c @@ -211,7 +211,8 @@ void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types, INP t_type_ptr types, INP int L_nx, INP int L_ny, INP struct s_grid_tile **L_grid, INP int chan_width, INP struct s_chan_width_dist *chan_capacity_inf, - INP enum e_switch_block_type sb_type, INP int Fs, INP int num_seg_types, + INP enum e_switch_block_type sb_type, INP int Fs, + INP enum e_switch_block_type sb_sub_type, INP int sub_Fs, INP int num_seg_types, INP int num_switches, INP t_segment_inf * segment_inf, INP int global_route_switch, INP int delayless_switch, INP t_timing_inf timing_inf, INP int wire_to_ipin_switch, @@ -225,7 +226,9 @@ void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types, build_tileable_unidir_rr_graph(L_num_types, types, L_nx, L_ny, L_grid, chan_width, - sb_type, Fs, num_seg_types, segment_inf, + sb_type, Fs, + sb_sub_type, sub_Fs, + num_seg_types, segment_inf, num_switches, delayless_switch, timing_inf, wire_to_ipin_switch, base_cost_type, directs, num_directs, ignore_Fc_0, Warnings); diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph.h b/vpr7_x2p/vpr/SRC/route/rr_graph.h index 9e23b0187..1a84393b7 100755 --- a/vpr7_x2p/vpr/SRC/route/rr_graph.h +++ b/vpr7_x2p/vpr/SRC/route/rr_graph.h @@ -28,6 +28,7 @@ void build_rr_graph(INP t_graph_type graph_type, INP struct s_chan_width_dist *chan_capacity_inf, INP enum e_switch_block_type sb_type, INP int Fs, + INP enum e_switch_block_type sb_sub_type, INP int sub_Fs, INP int num_seg_types, INP int num_switches, INP t_segment_inf * segment_inf,