From 9556f994b4d291593d0bafdf3a4aab11887df73e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Jun 2021 17:49:40 -0600 Subject: [PATCH] [Test] Use 'write_full_testbench' in all the memory bank -related test cases --- .../full_testbench/fast_memory_bank/config/task.conf | 4 +++- .../full_testbench/fast_memory_bank_use_set/config/task.conf | 4 +++- .../basic_tests/full_testbench/memory_bank/config/task.conf | 4 +++- .../full_testbench/memory_bank_use_reset/config/task.conf | 4 +++- .../full_testbench/memory_bank_use_resetb/config/task.conf | 4 +++- .../full_testbench/memory_bank_use_set/config/task.conf | 4 +++- .../full_testbench/memory_bank_use_set_reset/config/task.conf | 4 +++- .../full_testbench/memory_bank_use_setb/config/task.conf | 4 +++- .../full_testbench/multi_region_memory_bank/config/task.conf | 3 ++- .../full_testbench/smart_fast_memory_bank/config/task.conf | 4 +++- .../smart_fast_multi_region_memory_bank/config/task.conf | 4 +++- 11 files changed, 32 insertions(+), 11 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf index 5510c7a8c..c8789b46a 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf index 1ceeb3384..03c0b97ed 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf index 960cc0358..bd08da556 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf index 88f00dd83..d20ef4ee8 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf index 2db9c982f..502cd68ae 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf index 1b27c683c..33ea7546f 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf index 1e15dba22..52e103c6f 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf index 6f166e5fc..1ea736ca9 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf index 41c819a8c..20914980b 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf @@ -16,10 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf index f7e99fd89..b7368ad66 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf index 66d4da4fb..29fcb228d 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_bank_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml