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[core] format

This commit is contained in:
tangxifan 2023-03-05 22:32:05 -08:00
parent de1e300ec7
commit 953625b1ca
4 changed files with 77 additions and 58 deletions
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8
libs/libclkarchopenfpga/src/base/clock_network.cpp
View File

@ -129,7 +129,9 @@ size_t ClockNetwork::num_tracks(const ClockTreeId& tree_id,
continue; continue;
} }
if (spine_track_type(curr_spine) == track_type) { if (spine_track_type(curr_spine) == track_type) {
/* TODO: Deposit routing tracks in both INC and DEC direction, currently this is limited by the connection block build-up algorithm in fabric generator */ /* TODO: Deposit routing tracks in both INC and DEC direction, currently
* this is limited by the connection block build-up algorithm in fabric
* generator */
return 2 * tree_width(spine_parent_trees_[curr_spine]); return 2 * tree_width(spine_parent_trees_[curr_spine]);
} }
} }
@ -152,7 +154,9 @@ size_t ClockNetwork::num_tracks(const ClockTreeId& tree_id,
} }
if (spine_track_type(curr_spine) == track_type) { if (spine_track_type(curr_spine) == track_type) {
if (spine_direction(curr_spine) == direction) { if (spine_direction(curr_spine) == direction) {
/* TODO: Deposit routing tracks in both INC and DEC direction, currently this is limited by the connection block build-up algorithm in fabric generator */ /* TODO: Deposit routing tracks in both INC and DEC direction, currently
* this is limited by the connection block build-up algorithm in fabric
* generator */
return tree_width(spine_parent_trees_[curr_spine]); return tree_width(spine_parent_trees_[curr_spine]);
} }
} }

14
libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.cpp
View File

@ -49,7 +49,8 @@ RRNodeId RRClockSpatialLookup::find_node(int x, int y, const ClockTreeId& tree,
return RRNodeId::INVALID(); return RRNodeId::INVALID();
} }
if (size_t(pin) == rr_node_indices_[dir][x][y][size_t(tree)][size_t(lvl)].size()) { if (size_t(pin) ==
rr_node_indices_[dir][x][y][size_t(tree)][size_t(lvl)].size()) {
VTR_LOG("Pin id out of range"); VTR_LOG("Pin id out of range");
return RRNodeId::INVALID(); return RRNodeId::INVALID();
} }
@ -76,17 +77,17 @@ void RRClockSpatialLookup::add_node(RRNodeId node, int x, int y,
rr_node_indices_[dir][x][y][size_t(tree)].resize(size_t(lvl) + 1); rr_node_indices_[dir][x][y][size_t(tree)].resize(size_t(lvl) + 1);
} }
if (size_t(pin) >= rr_node_indices_[dir][x][y][size_t(tree)][size_t(lvl)].size()) { if (size_t(pin) >=
rr_node_indices_[dir][x][y][size_t(tree)][size_t(lvl)].resize(size_t(pin) + 1); rr_node_indices_[dir][x][y][size_t(tree)][size_t(lvl)].size()) {
rr_node_indices_[dir][x][y][size_t(tree)][size_t(lvl)].resize(size_t(pin) +
1);
} }
/* Resize on demand finished; Register the node */ /* Resize on demand finished; Register the node */
rr_node_indices_[dir][x][y][size_t(tree)][size_t(lvl)][size_t(pin)] = node; rr_node_indices_[dir][x][y][size_t(tree)][size_t(lvl)][size_t(pin)] = node;
} }
void RRClockSpatialLookup::reserve_nodes(int x, int y, void RRClockSpatialLookup::reserve_nodes(int x, int y, int tree, int lvl,
int tree,
int lvl,
int pin) { int pin) {
for (Direction dir : {Direction::INC, Direction::DEC}) { for (Direction dir : {Direction::INC, Direction::DEC}) {
resize_nodes(x, y, dir); resize_nodes(x, y, dir);
@ -104,7 +105,6 @@ void RRClockSpatialLookup::reserve_nodes(int x, int y,
} }
} }
void RRClockSpatialLookup::resize_nodes(int x, int y, void RRClockSpatialLookup::resize_nodes(int x, int y,
const Direction& direction) { const Direction& direction) {
/* Expand the fast look-up if the new node is out-of-range /* Expand the fast look-up if the new node is out-of-range

10
libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.h
View File

@ -89,10 +89,7 @@ class RRClockSpatialLookup {
* @brief Allocate memory for the lookup with maximum sizes on each dimension * @brief Allocate memory for the lookup with maximum sizes on each dimension
* .. note:: Must run before any other API! * .. note:: Must run before any other API!
*/ */
void reserve_nodes(int x, int y, void reserve_nodes(int x, int y, int tree, int lvl, int pin);
int tree,
int lvl,
int pin);
/** @brief Clear all the data inside */ /** @brief Clear all the data inside */
void clear(); void clear();
@ -106,10 +103,7 @@ class RRClockSpatialLookup {
/* Fast look-up: /* Fast look-up:
* [INC|DEC][0..grid_width][0..grid_height][tree_id][level_id][clock_pin_id] * [INC|DEC][0..grid_width][0..grid_height][tree_id][level_id][clock_pin_id]
*/ */
std::array< std::array<vtr::NdMatrix<std::vector<std::vector<std::vector<RRNodeId>>>, 2>,
vtr::NdMatrix<
std::vector<std::vector<std::vector<RRNodeId>>>,
2>,
2> 2>
rr_node_indices_; rr_node_indices_;
}; };

81
openfpga/src/annotation/append_clock_rr_graph.cpp
View File

@ -84,14 +84,11 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids,
* For each tree and level of the tree, add a number of clock nodes * For each tree and level of the tree, add a number of clock nodes
* with direction, ptc and coordinates etc. * with direction, ptc and coordinates etc.
*******************************************************************/ *******************************************************************/
static void add_rr_graph_block_clock_nodes(RRGraphBuilder& rr_graph_builder, static void add_rr_graph_block_clock_nodes(
RRClockSpatialLookup& clk_rr_lookup, RRGraphBuilder& rr_graph_builder, RRClockSpatialLookup& clk_rr_lookup,
const RRGraphView& rr_graph_view, const RRGraphView& rr_graph_view, const ClockNetwork& clk_ntwk,
const ClockNetwork& clk_ntwk, const vtr::Point<size_t> chan_coord, const t_rr_type& chan_type,
const vtr::Point<size_t> chan_coord, const int& cost_index_offset, const bool& verbose) {
const t_rr_type& chan_type,
const int& cost_index_offset,
const bool& verbose) {
size_t orig_chan_width = size_t orig_chan_width =
rr_graph_view.node_lookup() rr_graph_view.node_lookup()
.find_channel_nodes(chan_coord.x(), chan_coord.y(), chan_type) .find_channel_nodes(chan_coord.x(), chan_coord.y(), chan_type)
@ -100,8 +97,9 @@ static void add_rr_graph_block_clock_nodes(RRGraphBuilder& rr_graph_builder,
for (auto itree : clk_ntwk.trees()) { for (auto itree : clk_ntwk.trees()) {
for (auto ilvl : clk_ntwk.levels(itree)) { for (auto ilvl : clk_ntwk.levels(itree)) {
/* As we want to keep uni-directional wires, clock routing tracks have to be in pairs. /* As we want to keep uni-directional wires, clock routing tracks have to
* Therefore, always add clock routing tracks in pair, even one of them is not required * be in pairs. Therefore, always add clock routing tracks in pair, even
* one of them is not required
*/ */
size_t num_pins = 0; size_t num_pins = 0;
bool require_complementary_pins = false; bool require_complementary_pins = false;
@ -129,8 +127,12 @@ static void add_rr_graph_block_clock_nodes(RRGraphBuilder& rr_graph_builder,
/* register the node to a dedicated lookup */ /* register the node to a dedicated lookup */
clk_rr_lookup.add_node(clk_node, chan_coord.x(), chan_coord.y(), clk_rr_lookup.add_node(clk_node, chan_coord.x(), chan_coord.y(),
itree, ilvl, ClockTreePinId(ipin), node_dir); itree, ilvl, ClockTreePinId(ipin), node_dir);
VTR_LOGV(verbose, "Added node '%lu' to clock node lookup (x='%lu' y='%lu' tree='%lu' level='%lu' pin='%lu' direction='%s')\n", VTR_LOGV(verbose,
size_t(clk_node), chan_coord.x(), chan_coord.y(), size_t(itree), size_t(ilvl), ipin, DIRECTION_STRING[size_t(node_dir)]); "Added node '%lu' to clock node lookup (x='%lu' y='%lu' "
"tree='%lu' level='%lu' pin='%lu' direction='%s')\n",
size_t(clk_node), chan_coord.x(), chan_coord.y(),
size_t(itree), size_t(ilvl), ipin,
DIRECTION_STRING[size_t(node_dir)]);
/* Update ptc count and go to next */ /* Update ptc count and go to next */
curr_node_ptc++; curr_node_ptc++;
} }
@ -151,7 +153,9 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder,
const ClockNetwork& clk_ntwk, const ClockNetwork& clk_ntwk,
const bool& verbose) { const bool& verbose) {
/* Pre-allocate memory: Must do otherwise data will be messed up! */ /* Pre-allocate memory: Must do otherwise data will be messed up! */
clk_rr_lookup.reserve_nodes(grids.width(), grids.height(), clk_ntwk.num_trees(), clk_ntwk.max_tree_depth(), clk_ntwk.max_tree_width()); clk_rr_lookup.reserve_nodes(grids.width(), grids.height(),
clk_ntwk.num_trees(), clk_ntwk.max_tree_depth(),
clk_ntwk.max_tree_width());
/* Add X-direction clock nodes */ /* Add X-direction clock nodes */
for (size_t iy = 0; iy < grids.height() - 1; ++iy) { for (size_t iy = 0; iy < grids.height() - 1; ++iy) {
@ -166,11 +170,14 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder,
add_rr_graph_block_clock_nodes(rr_graph_builder, clk_rr_lookup, add_rr_graph_block_clock_nodes(rr_graph_builder, clk_rr_lookup,
rr_graph_view, clk_ntwk, chanx_coord, rr_graph_view, clk_ntwk, chanx_coord,
CHANX, CHANX_COST_INDEX_START, verbose); CHANX, CHANX_COST_INDEX_START, verbose);
VTR_ASSERT(rr_graph_view.valid_node(clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC))); VTR_ASSERT(rr_graph_view.valid_node(
clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0),
ClockTreePinId(0), Direction::INC)));
} }
} }
VTR_ASSERT(rr_graph_view.valid_node(clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC))); VTR_ASSERT(rr_graph_view.valid_node(clk_rr_lookup.find_node(
1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC)));
/* Add Y-direction clock nodes */ /* Add Y-direction clock nodes */
for (size_t ix = 0; ix < grids.width() - 1; ++ix) { for (size_t ix = 0; ix < grids.width() - 1; ++ix) {
@ -184,11 +191,15 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder,
} }
add_rr_graph_block_clock_nodes( add_rr_graph_block_clock_nodes(
rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, chany_coord, rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, chany_coord,
CHANY, CHANX_COST_INDEX_START + rr_graph_view.num_rr_segments(), verbose); CHANY, CHANX_COST_INDEX_START + rr_graph_view.num_rr_segments(),
VTR_ASSERT(rr_graph_view.valid_node(clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC))); verbose);
VTR_ASSERT(rr_graph_view.valid_node(
clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0),
ClockTreePinId(0), Direction::INC)));
} }
} }
VTR_ASSERT(rr_graph_view.valid_node(clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC))); VTR_ASSERT(rr_graph_view.valid_node(clk_rr_lookup.find_node(
1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC)));
} }
/******************************************************************** /********************************************************************
@ -481,8 +492,12 @@ static void add_rr_graph_block_clock_edges(
/* find the driver clock node through lookup */ /* find the driver clock node through lookup */
RRNodeId src_node = clk_rr_lookup.find_node( RRNodeId src_node = clk_rr_lookup.find_node(
chan_coord.x(), chan_coord.y(), itree, ilvl, ipin, node_dir); chan_coord.x(), chan_coord.y(), itree, ilvl, ipin, node_dir);
VTR_LOGV(verbose, "Try to find node '%lu' from clock node lookup (x='%lu' y='%lu' tree='%lu' level='%lu' pin='%lu' direction='%s')\n", VTR_LOGV(verbose,
size_t(src_node), chan_coord.x(), chan_coord.y(), size_t(itree), size_t(ilvl), size_t(ipin), DIRECTION_STRING[size_t(node_dir)]); "Try to find node '%lu' from clock node lookup (x='%lu' "
"y='%lu' tree='%lu' level='%lu' pin='%lu' direction='%s')\n",
size_t(src_node), chan_coord.x(), chan_coord.y(),
size_t(itree), size_t(ilvl), size_t(ipin),
DIRECTION_STRING[size_t(node_dir)]);
VTR_ASSERT(rr_graph_view.valid_node(src_node)); VTR_ASSERT(rr_graph_view.valid_node(src_node));
if (!clk_ntwk.is_last_level(itree, ilvl)) { if (!clk_ntwk.is_last_level(itree, ilvl)) {
/* find the fan-out clock node through lookup */ /* find the fan-out clock node through lookup */
@ -539,14 +554,11 @@ static void add_rr_graph_block_clock_edges(
* v * v
* clk0_lvl1_chany[1][1] * clk0_lvl1_chany[1][1]
*******************************************************************/ *******************************************************************/
static void add_rr_graph_clock_edges(RRGraphBuilder& rr_graph_builder, static void add_rr_graph_clock_edges(
size_t& num_edges_to_create, RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create,
const RRClockSpatialLookup& clk_rr_lookup, const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view,
const RRGraphView& rr_graph_view, const DeviceGrid& grids, const bool& through_channel,
const DeviceGrid& grids, const ClockNetwork& clk_ntwk, const bool& verbose) {
const bool& through_channel,
const ClockNetwork& clk_ntwk,
const bool& verbose) {
/* Add edges which is driven by X-direction clock routing tracks */ /* Add edges which is driven by X-direction clock routing tracks */
for (size_t iy = 0; iy < grids.height() - 1; ++iy) { for (size_t iy = 0; iy < grids.height() - 1; ++iy) {
for (size_t ix = 1; ix < grids.width() - 1; ++ix) { for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
@ -625,7 +637,8 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
/* Add clock nodes */ /* Add clock nodes */
add_rr_graph_clock_nodes(vpr_device_ctx.rr_graph_builder, clk_rr_lookup, add_rr_graph_clock_nodes(vpr_device_ctx.rr_graph_builder, clk_rr_lookup,
vpr_device_ctx.rr_graph, vpr_device_ctx.grid, vpr_device_ctx.rr_graph, vpr_device_ctx.grid,
vpr_device_ctx.arch->through_channel, clk_ntwk, verbose); vpr_device_ctx.arch->through_channel, clk_ntwk,
verbose);
VTR_LOGV(verbose, VTR_LOGV(verbose,
"Added %lu clock nodes to routing " "Added %lu clock nodes to routing "
"resource graph.\n", "resource graph.\n",
@ -640,14 +653,22 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
static_cast<const RRClockSpatialLookup&>(clk_rr_lookup), static_cast<const RRClockSpatialLookup&>(clk_rr_lookup),
vpr_device_ctx.rr_graph, vpr_device_ctx.grid, vpr_device_ctx.rr_graph, vpr_device_ctx.grid,
vpr_device_ctx.arch->through_channel, clk_ntwk, verbose); vpr_device_ctx.arch->through_channel, clk_ntwk, verbose);
VTR_LOGV(verbose,
"Added %lu clock edges to routing "
"resource graph.\n",
num_clock_edges);
/* TODO: Sanity checks */ /* TODO: Sanity checks */
VTR_LOGV(verbose, "Initializing fan-in of nodes\n");
vpr_device_ctx.rr_graph_builder.init_fan_in(); vpr_device_ctx.rr_graph_builder.init_fan_in();
VTR_LOGV(verbose, "Apply edge partitioning\n");
vpr_device_ctx.rr_graph_builder.partition_edges(); vpr_device_ctx.rr_graph_builder.partition_edges();
VTR_LOGV(verbose, "Building incoming edges\n");
vpr_device_ctx.rr_graph_builder.build_in_edges(); vpr_device_ctx.rr_graph_builder.build_in_edges();
/* Report number of added clock nodes and edges */ /* Report number of added clock nodes and edges */
VTR_LOG("Appended %lu clock nodes (+%.2f%) and %lu clock edges to routing " VTR_LOG(
"Appended %lu clock nodes (+%.2f%) and %lu clock edges to routing "
"resource graph.\n", "resource graph.\n",
num_clock_nodes, (float)(num_clock_nodes / orig_num_nodes), num_clock_nodes, (float)(num_clock_nodes / orig_num_nodes),
num_clock_edges); num_clock_edges);