diff --git a/openfpga/src/utils/physical_pb_utils.cpp b/openfpga/src/utils/physical_pb_utils.cpp
index 150028815..29a2164d2 100644
--- a/openfpga/src/utils/physical_pb_utils.cpp
+++ b/openfpga/src/utils/physical_pb_utils.cpp
@@ -191,12 +191,13 @@ static void synchronize_primitive_physical_pb_atom_nets(
       t_model_ports* model_port =
         pb_graph_node->input_pins[iport][ipin].port->model_port;
       /* Special for LUTs, the model port is hidden under 1 level */
-      if (LUT_CLASS == pb_graph_node->pb_type->class_type) {
-        VTR_ASSERT(pb_graph_node->pb_type->num_modes == 2);
-        model_port = pb_graph_node->child_pb_graph_nodes[1][0][0]
-                       .input_pins[iport][ipin]
-                       .port->model_port;
-      }
+      // Do NOT do this. Net mapping on LUT inputs may be swapped during rerouting
+      //if (LUT_CLASS == pb_graph_node->pb_type->class_type) {
+      //  VTR_ASSERT(pb_graph_node->pb_type->num_modes == 2);
+      //  model_port = pb_graph_node->child_pb_graph_nodes[1][0][0]
+      //                 .input_pins[iport][ipin]
+      //                 .port->model_port;
+      //}
       /* It seems that LUT port are no longer built with an internal model */
       if (nullptr == model_port) {
         VTR_LOGV(verbose, "Skip due to empty model port\n");
@@ -228,12 +229,13 @@ static void synchronize_primitive_physical_pb_atom_nets(
       t_model_ports* model_port =
         pb_graph_node->output_pins[iport][ipin].port->model_port;
       /* Special for LUTs, the model port is hidden under 1 level */
-      if (LUT_CLASS == pb_graph_node->pb_type->class_type) {
-        VTR_ASSERT(pb_graph_node->pb_type->num_modes == 2);
-        model_port = pb_graph_node->child_pb_graph_nodes[1][0][0]
-                       .output_pins[iport][ipin]
-                       .port->model_port;
-      }
+      // Do NOT do this. Net mapping on LUT inputs may be swapped during rerouting
+      //if (LUT_CLASS == pb_graph_node->pb_type->class_type) {
+      //  VTR_ASSERT(pb_graph_node->pb_type->num_modes == 2);
+      //  model_port = pb_graph_node->child_pb_graph_nodes[1][0][0]
+      //                 .output_pins[iport][ipin]
+      //                 .port->model_port;
+      //}
       if (nullptr == model_port) {
         VTR_LOGV(verbose, "Skip due to empty model port\n");
         continue;