From 93ab4b8dd29b50d5698300d201a98b10a1557090 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 26 Jan 2020 17:30:46 -0700
Subject: [PATCH] add test case for openfpga shell

---
 ...rac_N10_frac_chain_depop50_mem32K_40nm.xml |  1438 ++
 openfpga/test_blif/riscv_core_lut6.blif       | 19187 ++++++++++++++++
 openfpga/test_script/riscv_core.openfpga      |     2 +
 3 files changed, 20627 insertions(+)
 create mode 100644 openfpga/test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
 create mode 100644 openfpga/test_blif/riscv_core_lut6.blif
 create mode 100644 openfpga/test_script/riscv_core.openfpga

diff --git a/openfpga/test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml b/openfpga/test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
new file mode 100644
index 000000000..4594c6496
--- /dev/null
+++ b/openfpga/test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
@@ -0,0 +1,1438 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="multiply">
+      <input_ports>
+        <port name="a" combinational_sink_ports="out"/>
+        <port name="b" combinational_sink_ports="out"/>
+      </input_ports>
+      <output_ports>
+        <port name="out"/>
+      </output_ports>
+    </model>
+    <model name="single_port_ram">
+      <input_ports>
+        <port name="we" clock="clk"/>
+        <!-- control -->
+        <port name="addr" clock="clk"/>
+        <!-- address lines -->
+        <port name="data" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="clk" is_clock="1"/>
+        <!-- memories are often clocked -->
+      </input_ports>
+      <output_ports>
+        <port name="out" clock="clk"/>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <port name="we1" clock="clk"/>
+        <!-- write enable -->
+        <port name="we2" clock="clk"/>
+        <!-- write enable -->
+        <port name="addr1" clock="clk"/>
+        <!-- address lines -->
+        <port name="addr2" clock="clk"/>
+        <!-- address lines -->
+        <port name="data1" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="data2" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="clk" is_clock="1"/>
+        <!-- memories are often clocked -->
+      </input_ports>
+      <output_ports>
+        <port name="out1" clock="clk"/>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="out2" clock="clk"/>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+      </output_ports>
+    </model>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <clock name="clock" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad io.clock</loc>
+        <loc side="top">io.outpad io.inpad io.clock</loc>
+        <loc side="right">io.outpad io.inpad io.clock</loc>
+        <loc side="bottom">io.outpad io.inpad io.clock</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I1" num_pins="13" equivalent="full"/>
+      <input name="I2" num_pins="13" equivalent="full"/>
+      <input name="I3" num_pins="13" equivalent="full"/>
+      <input name="I4" num_pins="13" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <pinlocations pattern="spread"/>
+    </tile>
+    <tile name="mult_36" height="4" area="396000">
+      <equivalent_sites>
+        <site pb_type="mult_36"/>
+      </equivalent_sites>
+      <input name="a" num_pins="36"/>
+      <input name="b" num_pins="36"/>
+      <output name="out" num_pins="72"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+    <tile name="memory" height="6" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="addr1" num_pins="15"/>
+      <input name="addr2" num_pins="15"/>
+      <input name="data" num_pins="64"/>
+      <input name="we1" num_pins="1"/>
+      <input name="we2" num_pins="1"/>
+      <output name="out" num_pins="64"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout>
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'mult_36' with 'EMPTY' blocks wherever a 'mult_36' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="mult_36" startx="6" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="6" repeatx="8" starty="1" priority="19"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </auto_layout>
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <segment freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <clock name="clock" num_pins="1"/>
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I1" num_pins="13" equivalent="full"/>
+      <input name="I2" num_pins="13" equivalent="full"/>
+      <input name="I3" num_pins="13" equivalent="full"/>
+      <input name="I4" num_pins="13" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="8"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <mode name="n2_lut5">
+          <pb_type name="lut5inter" num_pb="1">
+            <input name="in" num_pins="8"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble5" num_pb="2">
+              <input name="in" num_pins="5"/>
+              <input name="cin" num_pins="1"/>
+              <output name="out" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <mode name="blut5">
+                <pb_type name="flut5" num_pb="1">
+                  <input name="in" num_pins="5"/>
+                  <output name="out" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Regular LUT mode -->
+                  <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+                    <input name="in" num_pins="5" port_class="lut_in"/>
+                    <output name="out" num_pins="1" port_class="lut_out"/>
+                    <!-- LUT timing using delay matrix -->
+                    <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                           we instead take the average of these numbers to get more stable results
+                        82e-12
+                        173e-12
+                        261e-12
+                        263e-12
+                        398e-12
+                        -->
+                    <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                        235e-12
+                        235e-12
+                        235e-12
+                        235e-12
+                        235e-12
+                      </delay_matrix>
+                  </pb_type>
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="direct1" input="flut5.in" output="lut5.in"/>
+                    <direct name="direct2" input="lut5.out" output="ff.D">
+                      <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+                    </direct>
+                    <direct name="direct3" input="flut5.clk" output="ff.clk"/>
+                    <mux name="mux1" input="ff.Q lut5.out" output="flut5.out">
+                      <delay_constant max="25e-12" in_port="lut5.out" out_port="flut5.out"/>
+                      <delay_constant max="45e-12" in_port="ff.Q" out_port="flut5.out"/>
+                    </mux>
+                  </interconnect>
+                </pb_type>
+                <interconnect>
+                  <direct name="direct1" input="ble5.in" output="flut5.in"/>
+                  <direct name="direct2" input="ble5.clk" output="flut5.clk"/>
+                  <direct name="direct3" input="flut5.out" output="ble5.out"/>
+                </interconnect>
+              </mode>
+              <mode name="arithmetic">
+                <pb_type name="arithmetic" num_pb="1">
+                  <input name="in" num_pins="4"/>
+                  <input name="cin" num_pins="1"/>
+                  <output name="out" num_pins="1"/>
+                  <output name="cout" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Special dual-LUT mode that drives adder only -->
+                  <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+                    <input name="in" num_pins="4" port_class="lut_in"/>
+                    <output name="out" num_pins="1" port_class="lut_out"/>
+                    <!-- LUT timing using delay matrix -->
+                    <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                             we instead take the average of these numbers to get more stable results
+                        82e-12
+                        173e-12
+                        261e-12
+                        263e-12
+                        -->
+                    <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                        195e-12
+                        195e-12
+                        195e-12
+                        195e-12
+                      </delay_matrix>
+                  </pb_type>
+                  <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+                    <input name="a" num_pins="1"/>
+                    <input name="b" num_pins="1"/>
+                    <input name="cin" num_pins="1"/>
+                    <output name="cout" num_pins="1"/>
+                    <output name="sumout" num_pins="1"/>
+                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+                    <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+                  </pb_type>
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+                    <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+                    <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+                    <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                      </direct>
+                    <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                      </direct>
+                    <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                      <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+                    </direct>
+                    <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                      <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+                    </direct>
+                    <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                      <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+                    </direct>
+                    <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                      <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                      <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+                    </mux>
+                  </interconnect>
+                </pb_type>
+                <interconnect>
+                  <direct name="direct1" input="ble5.in[3:0]" output="arithmetic.in"/>
+                  <direct name="carry_in" input="ble5.cin" output="arithmetic.cin">
+                    <pack_pattern name="chain" in_port="ble5.cin" out_port="arithmetic.cin"/>
+                  </direct>
+                  <direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
+                    <pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/>
+                  </direct>
+                  <direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
+                  <direct name="direct3" input="arithmetic.out" output="ble5.out"/>
+                </interconnect>
+              </mode>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut5inter.in[4:0]" output="ble5[0:0].in"/>
+              <direct name="direct2" input="lut5inter.in[7:3]" output="ble5[1:1].in"/>
+              <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
+              <direct name="carry_in" input="lut5inter.cin" output="ble5[0:0].cin">
+                <pack_pattern name="chain" in_port="lut5inter.cin" out_port="ble5[0:0].cin"/>
+              </direct>
+              <direct name="carry_out" input="ble5[1:1].cout" output="lut5inter.cout">
+                <pack_pattern name="chain" in_port="ble5[1:1].cout" out_port="lut5inter.cout"/>
+              </direct>
+              <direct name="carry_link" input="ble5[0:0].cout" output="ble5[1:1].cin">
+                <pack_pattern name="chain" in_port="ble5[0:0].cout" out_port="ble5[1:1].cout"/>
+              </direct>
+              <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="lut5inter.in"/>
+            <direct name="direct2" input="lut5inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
+            <direct name="carry_in" input="fle.cin" output="lut5inter.cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="lut5inter.cin"/>
+            </direct>
+            <direct name="carry_out" input="lut5inter.cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="lut5inter.cout" out_port="fle.cout"/>
+            </direct>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <!-- 50% sparsely populated local routing -->
+        <complete name="lutA" input="clb.I4 clb.I3 fle[1:0].out fle[3:2].out fle[8:8].out" output="fle[9:0].in[0:0]">
+          <delay_constant max="95e-12" in_port="clb.I4" out_port="fle.in[0:0]"/>
+          <delay_constant max="95e-12" in_port="clb.I3" out_port="fle.in[0:0]"/>
+          <delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle.in[0:0]"/>
+          <delay_constant max="75e-12" in_port="fle[3:2].out" out_port="fle.in[0:0]"/>
+          <delay_constant max="75e-12" in_port="fle[8:8].out" out_port="fle.in[0:0]"/>
+        </complete>
+        <complete name="lutB" input="clb.I3 clb.I2 fle[3:2].out fle[5:4].out fle[9:9].out" output="fle[9:0].in[1:1]">
+          <delay_constant max="95e-12" in_port="clb.I3" out_port="fle.in[1:1]"/>
+          <delay_constant max="95e-12" in_port="clb.I2" out_port="fle.in[1:1]"/>
+          <delay_constant max="75e-12" in_port="fle[3:2].out" out_port="fle.in[1:1]"/>
+          <delay_constant max="75e-12" in_port="fle[5:4].out" out_port="fle.in[1:1]"/>
+          <delay_constant max="75e-12" in_port="fle[9:9].out" out_port="fle.in[1:1]"/>
+        </complete>
+        <complete name="lutC" input="clb.I2 clb.I1 fle[5:4].out fle[7:6].out fle[8:8].out" output="fle[9:0].in[2:2]">
+          <delay_constant max="95e-12" in_port="clb.I2" out_port="fle.in[2:2]"/>
+          <delay_constant max="95e-12" in_port="clb.I1" out_port="fle.in[2:2]"/>
+          <delay_constant max="75e-12" in_port="fle[5:4].out" out_port="fle.in[2:2]"/>
+          <delay_constant max="75e-12" in_port="fle[7:6].out" out_port="fle.in[2:2]"/>
+          <delay_constant max="75e-12" in_port="fle[8:8].out" out_port="fle.in[2:2]"/>
+        </complete>
+        <complete name="lutD" input="clb.I4 clb.I2 fle[1:0].out fle[5:4].out fle[9:9].out" output="fle[9:0].in[3:3]">
+          <delay_constant max="95e-12" in_port="clb.I4" out_port="fle.in[3:3]"/>
+          <delay_constant max="95e-12" in_port="clb.I2" out_port="fle.in[3:3]"/>
+          <delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle.in[3:3]"/>
+          <delay_constant max="75e-12" in_port="fle[5:4].out" out_port="fle.in[3:3]"/>
+          <delay_constant max="75e-12" in_port="fle[9:9].out" out_port="fle.in[3:3]"/>
+        </complete>
+        <complete name="lutE" input="clb.I3 clb.I1 fle[3:2].out fle[7:6].out fle[8:8].out" output="fle[9:0].in[4:4]">
+          <delay_constant max="95e-12" in_port="clb.I3" out_port="fle.in[4:4]"/>
+          <delay_constant max="95e-12" in_port="clb.I1" out_port="fle.in[4:4]"/>
+          <delay_constant max="75e-12" in_port="fle[3:2].out" out_port="fle.in[4:4]"/>
+          <delay_constant max="75e-12" in_port="fle[7:6].out" out_port="fle.in[4:4]"/>
+          <delay_constant max="75e-12" in_port="fle[8:8].out" out_port="fle.in[4:4]"/>
+        </complete>
+        <complete name="lutF" input="clb.I4 clb.I1 fle[1:0].out fle[7:6].out fle[9:9].out" output="fle[9:0].in[5:5]">
+          <delay_constant max="95e-12" in_port="clb.I4" out_port="fle.in[5:5]"/>
+          <delay_constant max="95e-12" in_port="clb.I1" out_port="fle.in[5:5]"/>
+          <delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle.in[5:5]"/>
+          <delay_constant max="75e-12" in_port="fle[7:6].out" out_port="fle.in[5:5]"/>
+          <delay_constant max="75e-12" in_port="fle[9:9].out" out_port="fle.in[5:5]"/>
+        </complete>
+        <complete name="lutG" input="clb.I4 clb.I3 fle[1:0].out fle[3:2].out fle[8:8].out" output="fle[9:0].in[6:6]">
+          <delay_constant max="95e-12" in_port="clb.I4" out_port="fle.in[6:6]"/>
+          <delay_constant max="95e-12" in_port="clb.I3" out_port="fle.in[6:6]"/>
+          <delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle.in[6:6]"/>
+          <delay_constant max="75e-12" in_port="fle[3:2].out" out_port="fle.in[6:6]"/>
+          <delay_constant max="75e-12" in_port="fle[8:8].out" out_port="fle.in[6:6]"/>
+        </complete>
+        <complete name="lutH" input="clb.I3 clb.I2 fle[3:2].out fle[5:4].out fle[9:9].out" output="fle[9:0].in[7:7]">
+          <delay_constant max="95e-12" in_port="clb.I3" out_port="fle.in[7:7]"/>
+          <delay_constant max="95e-12" in_port="clb.I2" out_port="fle.in[7:7]"/>
+          <delay_constant max="75e-12" in_port="fle[3:2].out" out_port="fle.in[7:7]"/>
+          <delay_constant max="75e-12" in_port="fle[5:4].out" out_port="fle.in[7:7]"/>
+          <delay_constant max="75e-12" in_port="fle[9:9].out" out_port="fle.in[7:7]"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+          </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define fracturable multiplier begin -->
+    <!-- This multiplier can operate as a 36x36 multiplier that can fracture to two 18x18 multipliers each of which can further fracture to two 9x9 multipliers 
+	   For delay modelling, the 36x36 DSP multiplier in Stratix IV has a delay of 1.523 ns + 1.93 ns
+	    = 3.45 ns. The 18x18 mode doesn't need to sum four 18x18 multipliers, so it is a bit
+	   faster: 1.523 ns for the multiplier, and 1.09 ns for the multiplier output block.
+	    For the input and output interconnect delays, unlike Stratix IV, we don't
+	   have any routing/logic flexibility (crossbars) at the inputs.  There is some output muxing
+	   in Stratix IV and this architecture to select which multiplier outputs should go out (e.g.
+	   9x9 outputs, 18x18 or 36x36) so those are very close between the two architectures. 
+	   We take the conservative (slightly pessimistic)
+           approach modelling the input as the same as the Stratix IV input delay and the output delay the same as the Stratix IV DSP out delay.
+		   
+	   We estimate block area by using the published Stratix III data (which is architecturally identical to Stratix IV)
+	      (H. Wong, V. Betz and J. Rose, "Comparing FPGA vs. Custom CMOS and the Impact on Processor Microarchitecture", FPGA 2011) of 0.2623 
+		  mm^2 and scaling from 65 to 40 nm to obtain 0.0993 mm^2. That area is for a DSP block with approximately 2x the functionality of 
+		  the block we use (can implement two 36x36 multiplies instead of our 1, eight 18x18 multiplies instead of our 4, etc.). Hence we 
+		  divide the area by 2 to obtain 0.0497 mm^2. One minimum-width transistor units = 60 L^2 (where L = 40 nm), so is 518,000 MWTUS. 
+		  That area includes routing and the connection block input muxes.  Our DSP block is four 
+		  rows high, and hence includes four horizontal routing channel segments and four vertical ones, which is 4x the routing of a logic 
+		  block (single tile). It also includes 3.6x the outputs of a logic block, and 1.8x the inputs. Hence a slight overestimate of the routing
+		  area associated with our DSP block is four times that of a logic tile, where the routing area of a logic tile was calculated above (at W = 300)
+		  as 30481 MWTAs. Hence the (core, non-routing) area our DSP block is approximately 518,000 - 4 * 30,481 = 396,000 MWTUs.
+      -->
+    <pb_type name="mult_36">
+      <input name="a" num_pins="36"/>
+      <input name="b" num_pins="36"/>
+      <output name="out" num_pins="72"/>
+      <mode name="two_divisible_mult_18x18">
+        <pb_type name="divisible_mult_18x18" num_pb="2">
+          <input name="a" num_pins="18"/>
+          <input name="b" num_pins="18"/>
+          <output name="out" num_pins="36"/>
+          <!-- Model 9x9 delay and 18x18 delay as the same.  9x9 could be faster, but in Stratix IV
+	          isn't, presumably because the multiplier layout is really optimized for 18x18.
+		-->
+          <mode name="two_mult_9x9">
+            <pb_type name="mult_9x9_slice" num_pb="2">
+              <input name="A_cfg" num_pins="9"/>
+              <input name="B_cfg" num_pins="9"/>
+              <output name="OUT_cfg" num_pins="18"/>
+              <pb_type name="mult_9x9" blif_model=".subckt multiply" num_pb="1">
+                <input name="a" num_pins="9"/>
+                <input name="b" num_pins="9"/>
+                <output name="out" num_pins="18"/>
+                <delay_constant max="1.523e-9" in_port="mult_9x9.a" out_port="mult_9x9.out"/>
+                <delay_constant max="1.523e-9" in_port="mult_9x9.b" out_port="mult_9x9.out"/>
+              </pb_type>
+              <interconnect>
+                <direct name="a2a" input="mult_9x9_slice.A_cfg" output="mult_9x9.a">
+                </direct>
+                <direct name="b2b" input="mult_9x9_slice.B_cfg" output="mult_9x9.b">
+                </direct>
+                <direct name="out2out" input="mult_9x9.out" output="mult_9x9_slice.OUT_cfg">
+                </direct>
+              </interconnect>
+              <power method="pin-toggle">
+                <port name="A_cfg" energy_per_toggle="1.45e-12"/>
+                <port name="B_cfg" energy_per_toggle="1.45e-12"/>
+                <static_power power_per_instance="0.0"/>
+              </power>
+            </pb_type>
+            <interconnect>
+              <direct name="a2a" input="divisible_mult_18x18.a" output="mult_9x9_slice[1:0].A_cfg">
+              </direct>
+              <direct name="b2b" input="divisible_mult_18x18.b" output="mult_9x9_slice[1:0].B_cfg">
+              </direct>
+              <direct name="out2out" input="mult_9x9_slice[1:0].OUT_cfg" output="divisible_mult_18x18.out">
+              </direct>
+            </interconnect>
+          </mode>
+          <mode name="mult_18x18">
+            <pb_type name="mult_18x18_slice" num_pb="1">
+              <input name="A_cfg" num_pins="18"/>
+              <input name="B_cfg" num_pins="18"/>
+              <output name="OUT_cfg" num_pins="36"/>
+              <pb_type name="mult_18x18" blif_model=".subckt multiply" num_pb="1">
+                <input name="a" num_pins="18"/>
+                <input name="b" num_pins="18"/>
+                <output name="out" num_pins="36"/>
+                <delay_constant max="1.523e-9" in_port="mult_18x18.a" out_port="mult_18x18.out"/>
+                <delay_constant max="1.523e-9" in_port="mult_18x18.b" out_port="mult_18x18.out"/>
+              </pb_type>
+              <interconnect>
+                <direct name="a2a" input="mult_18x18_slice.A_cfg" output="mult_18x18.a">
+                </direct>
+                <direct name="b2b" input="mult_18x18_slice.B_cfg" output="mult_18x18.b">
+                </direct>
+                <direct name="out2out" input="mult_18x18.out" output="mult_18x18_slice.OUT_cfg">
+                </direct>
+              </interconnect>
+              <power method="pin-toggle">
+                <port name="A_cfg" energy_per_toggle="1.09e-12"/>
+                <port name="B_cfg" energy_per_toggle="1.09e-12"/>
+                <static_power power_per_instance="0.0"/>
+              </power>
+            </pb_type>
+            <interconnect>
+              <direct name="a2a" input="divisible_mult_18x18.a" output="mult_18x18_slice.A_cfg">
+              </direct>
+              <direct name="b2b" input="divisible_mult_18x18.b" output="mult_18x18_slice.B_cfg">
+              </direct>
+              <direct name="out2out" input="mult_18x18_slice.OUT_cfg" output="divisible_mult_18x18.out">
+              </direct>
+            </interconnect>
+          </mode>
+          <power method="sum-of-children"/>
+        </pb_type>
+        <interconnect>
+          <!-- Stratix IV input delay of 207ps is conservative for this architecture because this architecture does not have an input crossbar in the multiplier. 
+		   Subtract 72.5 ps delay, which is already in the connection block input mux, leading
+              -->
+          <direct name="a2a" input="mult_36.a" output="divisible_mult_18x18[1:0].a">
+            <delay_constant max="134e-12" in_port="mult_36.a" out_port="divisible_mult_18x18[1:0].a"/>
+          </direct>
+          <direct name="b2b" input="mult_36.b" output="divisible_mult_18x18[1:0].b">
+            <delay_constant max="134e-12" in_port="mult_36.b" out_port="divisible_mult_18x18[1:0].b"/>
+          </direct>
+          <direct name="out2out" input="divisible_mult_18x18[1:0].out" output="mult_36.out">
+            <delay_constant max="1.09e-9" in_port="divisible_mult_18x18[1:0].out" out_port="mult_36.out"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mult_36x36">
+        <pb_type name="mult_36x36_slice" num_pb="1">
+          <input name="A_cfg" num_pins="36"/>
+          <input name="B_cfg" num_pins="36"/>
+          <output name="OUT_cfg" num_pins="72"/>
+          <pb_type name="mult_36x36" blif_model=".subckt multiply" num_pb="1">
+            <input name="a" num_pins="36"/>
+            <input name="b" num_pins="36"/>
+            <output name="out" num_pins="72"/>
+            <delay_constant max="1.523e-9" in_port="mult_36x36.a" out_port="mult_36x36.out"/>
+            <delay_constant max="1.523e-9" in_port="mult_36x36.b" out_port="mult_36x36.out"/>
+          </pb_type>
+          <interconnect>
+            <direct name="a2a" input="mult_36x36_slice.A_cfg" output="mult_36x36.a">
+            </direct>
+            <direct name="b2b" input="mult_36x36_slice.B_cfg" output="mult_36x36.b">
+            </direct>
+            <direct name="out2out" input="mult_36x36.out" output="mult_36x36_slice.OUT_cfg">
+            </direct>
+          </interconnect>
+          <power method="pin-toggle">
+            <port name="A_cfg" energy_per_toggle="2.13e-12"/>
+            <port name="B_cfg" energy_per_toggle="2.13e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <!-- Stratix IV input delay of 207ps is conservative for this architecture because this architecture does not have an input crossbar in the multiplier. 
+		   Subtract 72.5 ps delay, which is already in the connection block input mux, leading
+		   to a 134 ps delay.
+              -->
+          <direct name="a2a" input="mult_36.a" output="mult_36x36_slice.A_cfg">
+            <delay_constant max="134e-12" in_port="mult_36.a" out_port="mult_36x36_slice.A_cfg"/>
+          </direct>
+          <direct name="b2b" input="mult_36.b" output="mult_36x36_slice.B_cfg">
+            <delay_constant max="134e-12" in_port="mult_36.b" out_port="mult_36x36_slice.B_cfg"/>
+          </direct>
+          <direct name="out2out" input="mult_36x36_slice.OUT_cfg" output="mult_36.out">
+            <delay_constant max="1.93e-9" in_port="mult_36x36_slice.OUT_cfg" out_port="mult_36.out"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Place this multiplier block every 8 columns from (and including) the sixth column -->
+      <power method="sum-of-children"/>
+    </pb_type>
+    <!-- Define fracturable multiplier end -->
+    <!-- Define fracturable memory begin -->
+    <!-- 32 Kb Memory that can operate from 512x64 to 32Kx1 for single-port mode and 1024x32 to 32Kx1 for dual-port mode.  
+           Area and delay based off Stratix IV 9K and 144K memories (delay from linear interpolation, Tsu(483 ps, 636 ps) Tco(1084ps, 1969ps)).  
+           Input delay = 204ps (from Stratix IV LAB line) - 72ps (this architecture does not lump connection box delay in internal delay)
+           Output delay = M9K buffer 50ps
+		   
+		   Area is obtained by appropriately scaling and adjusting the published Stratix III (which is architecturally identical to Stratix IV)
+		   data from H. Wong, V. Betz and J. Rose, "Comparing FPGA vs. Custom CMOS and the Impact on Processor Microarchitecture", FPGA 2011.
+		   Linearly interpolating (by bit count) between the M9k and M144k areas to obtain an M32k (our RAM size) point yields a 65 nm area of
+		   of 0.153 mm^2. Interpolating based on port count between the RAMs would instead yield an area of 0.209 mm^2 for our 32 kB RAM; since 
+		   bit count accounts for more area than ports for a RAM this size we choose the bit count interpolation; however, since the port interpolation
+		   is not radically different this also gives us confidence that interpolating based on bits is OK, but slightly underpredicts area.
+		   Scaling to 40 nm^2 yields .0579 mm^2, and converting to MWTUs at 60 L^2 / MWTU yields 604,000 MWTUs. This includes routing. A Stratix IV
+		   M9K RAM is one row high and hence has one routing tile (one horizonal and one vertical routing segment area). An M144k RAM has 8 such tiles.
+		   Linearly interpolating on
+		   bits to 32 kb yields 2.2 routing tiles incorporated in the area number above. The inter-block routing represents 30% of the area of a logic 
+		   tile according to D. Lewis et al, "Architectural Enhancements in Stratix V," FPGA 2013. Hence we should subtract 0.3 * 2.2 * 84,375 MWTUs to
+		   obtain a RAM core area (not including inter-block routing) of 548,000 MWTU areas for our 32 kb RAM in a 40 nm process.
+      -->
+    <pb_type name="memory">
+      <input name="addr1" num_pins="15"/>
+      <input name="addr2" num_pins="15"/>
+      <input name="data" num_pins="64"/>
+      <input name="we1" num_pins="1"/>
+      <input name="we2" num_pins="1"/>
+      <output name="out" num_pins="64"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify single port mode first -->
+      <mode name="mem_512x64_sp">
+        <pb_type name="mem_512x64_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="9" port_class="address"/>
+          <input name="data" num_pins="64" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="64" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x64_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x64_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x64_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x64_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[8:0]" output="mem_512x64_sp.addr">
+            <delay_constant max="132e-12" in_port="memory.addr1[8:0]" out_port="mem_512x64_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[63:0]" output="mem_512x64_sp.data">
+            <delay_constant max="132e-12" in_port="memory.data[63:0]" out_port="mem_512x64_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_512x64_sp.we">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_512x64_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_512x64_sp.out" output="memory.out[63:0]">
+            <delay_constant max="40e-12" in_port="mem_512x64_sp.out" out_port="memory.out[63:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x64_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_1024x32_sp">
+        <pb_type name="mem_1024x32_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="10" port_class="address"/>
+          <input name="data" num_pins="32" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_1024x32_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_1024x32_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[9:0]" output="mem_1024x32_sp.addr">
+            <delay_constant max="132e-12" in_port="memory.addr1[9:0]" out_port="mem_1024x32_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[31:0]" output="mem_1024x32_sp.data">
+            <delay_constant max="132e-12" in_port="memory.data[31:0]" out_port="mem_1024x32_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_1024x32_sp.we">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_1024x32_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_1024x32_sp.out" output="memory.out[31:0]">
+            <delay_constant max="40e-12" in_port="mem_1024x32_sp.out" out_port="memory.out[31:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_1024x32_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_2048x16_sp">
+        <pb_type name="mem_2048x16_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="11" port_class="address"/>
+          <input name="data" num_pins="16" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="16" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_2048x16_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_2048x16_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[10:0]" output="mem_2048x16_sp.addr">
+            <delay_constant max="132e-12" in_port="memory.addr1[10:0]" out_port="mem_2048x16_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[15:0]" output="mem_2048x16_sp.data">
+            <delay_constant max="132e-12" in_port="memory.data[15:0]" out_port="mem_2048x16_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_2048x16_sp.we">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_2048x16_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_2048x16_sp.out" output="memory.out[15:0]">
+            <delay_constant max="40e-12" in_port="mem_2048x16_sp.out" out_port="memory.out[15:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_2048x16_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_4096x8_sp">
+        <pb_type name="mem_4096x8_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="12" port_class="address"/>
+          <input name="data" num_pins="8" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="8" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_4096x8_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_4096x8_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_4096x8_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_4096x8_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[11:0]" output="mem_4096x8_sp.addr">
+            <delay_constant max="132e-12" in_port="memory.addr1[11:0]" out_port="mem_4096x8_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[7:0]" output="mem_4096x8_sp.data">
+            <delay_constant max="132e-12" in_port="memory.data[7:0]" out_port="mem_4096x8_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_4096x8_sp.we">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_4096x8_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_4096x8_sp.out" output="memory.out[7:0]">
+            <delay_constant max="40e-12" in_port="mem_4096x8_sp.out" out_port="memory.out[7:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_4096x8_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_8192x4_sp">
+        <pb_type name="mem_8192x4_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="13" port_class="address"/>
+          <input name="data" num_pins="4" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="4" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_8192x4_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_8192x4_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[12:0]" output="mem_8192x4_sp.addr">
+            <delay_constant max="132e-12" in_port="memory.addr1[12:0]" out_port="mem_8192x4_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[3:0]" output="mem_8192x4_sp.data">
+            <delay_constant max="132e-12" in_port="memory.data[3:0]" out_port="mem_8192x4_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_8192x4_sp.we">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_8192x4_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_8192x4_sp.out" output="memory.out[3:0]">
+            <delay_constant max="40e-12" in_port="mem_8192x4_sp.out" out_port="memory.out[3:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_8192x4_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_16384x2_sp">
+        <pb_type name="mem_16384x2_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="14" port_class="address"/>
+          <input name="data" num_pins="2" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="2" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_16384x2_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_16384x2_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[13:0]" output="mem_16384x2_sp.addr">
+            <delay_constant max="132e-12" in_port="memory.addr1[13:0]" out_port="mem_16384x2_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[1:0]" output="mem_16384x2_sp.data">
+            <delay_constant max="132e-12" in_port="memory.data[1:0]" out_port="mem_16384x2_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_16384x2_sp.we">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_16384x2_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_16384x2_sp.out" output="memory.out[1:0]">
+            <delay_constant max="40e-12" in_port="mem_16384x2_sp.out" out_port="memory.out[1:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_16384x2_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_32768x1_sp">
+        <pb_type name="mem_32768x1_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="15" port_class="address"/>
+          <input name="data" num_pins="1" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="1" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_32768x1_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_32768x1_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[14:0]" output="mem_32768x1_sp.addr">
+            <delay_constant max="132e-12" in_port="memory.addr1[14:0]" out_port="mem_32768x1_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[0:0]" output="mem_32768x1_sp.data">
+            <delay_constant max="132e-12" in_port="memory.data[0:0]" out_port="mem_32768x1_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_32768x1_sp.we">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_32768x1_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_32768x1_sp.out" output="memory.out[0:0]">
+            <delay_constant max="40e-12" in_port="mem_32768x1_sp.out" out_port="memory.out[0:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_32768x1_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Specify true dual port mode next -->
+      <mode name="mem_1024x32_dp">
+        <pb_type name="mem_1024x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="10" port_class="address1"/>
+          <input name="addr2" num_pins="10" port_class="address2"/>
+          <input name="data1" num_pins="32" port_class="data_in1"/>
+          <input name="data2" num_pins="32" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="32" port_class="data_out1"/>
+          <output name="out2" num_pins="32" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_1024x32_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_1024x32_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[9:0]" output="mem_1024x32_dp.addr1">
+            <delay_constant max="132e-12" in_port="memory.addr1[9:0]" out_port="mem_1024x32_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[9:0]" output="mem_1024x32_dp.addr2">
+            <delay_constant max="132e-12" in_port="memory.addr2[9:0]" out_port="mem_1024x32_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[31:0]" output="mem_1024x32_dp.data1">
+            <delay_constant max="132e-12" in_port="memory.data[31:0]" out_port="mem_1024x32_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[63:32]" output="mem_1024x32_dp.data2">
+            <delay_constant max="132e-12" in_port="memory.data[63:32]" out_port="mem_1024x32_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_1024x32_dp.we1">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_1024x32_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_1024x32_dp.we2">
+            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_1024x32_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_1024x32_dp.out1" output="memory.out[31:0]">
+            <delay_constant max="40e-12" in_port="mem_1024x32_dp.out1" out_port="memory.out[31:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_1024x32_dp.out2" output="memory.out[63:32]">
+            <delay_constant max="40e-12" in_port="mem_1024x32_dp.out2" out_port="memory.out[63:32]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_1024x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_2048x16_dp">
+        <pb_type name="mem_2048x16_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="11" port_class="address1"/>
+          <input name="addr2" num_pins="11" port_class="address2"/>
+          <input name="data1" num_pins="16" port_class="data_in1"/>
+          <input name="data2" num_pins="16" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="16" port_class="data_out1"/>
+          <output name="out2" num_pins="16" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_2048x16_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_2048x16_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[10:0]" output="mem_2048x16_dp.addr1">
+            <delay_constant max="132e-12" in_port="memory.addr1[10:0]" out_port="mem_2048x16_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[10:0]" output="mem_2048x16_dp.addr2">
+            <delay_constant max="132e-12" in_port="memory.addr2[10:0]" out_port="mem_2048x16_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[15:0]" output="mem_2048x16_dp.data1">
+            <delay_constant max="132e-12" in_port="memory.data[15:0]" out_port="mem_2048x16_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[31:16]" output="mem_2048x16_dp.data2">
+            <delay_constant max="132e-12" in_port="memory.data[31:16]" out_port="mem_2048x16_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_2048x16_dp.we1">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_2048x16_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_2048x16_dp.we2">
+            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_2048x16_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_2048x16_dp.out1" output="memory.out[15:0]">
+            <delay_constant max="40e-12" in_port="mem_2048x16_dp.out1" out_port="memory.out[15:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_2048x16_dp.out2" output="memory.out[31:16]">
+            <delay_constant max="40e-12" in_port="mem_2048x16_dp.out2" out_port="memory.out[31:16]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_2048x16_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_2048x8_dp">
+        <pb_type name="mem_2048x8_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="12" port_class="address1"/>
+          <input name="addr2" num_pins="12" port_class="address2"/>
+          <input name="data1" num_pins="8" port_class="data_in1"/>
+          <input name="data2" num_pins="8" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="8" port_class="data_out1"/>
+          <output name="out2" num_pins="8" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_2048x8_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x8_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x8_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x8_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x8_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x8_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_2048x8_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_2048x8_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[11:0]" output="mem_2048x8_dp.addr1">
+            <delay_constant max="132e-12" in_port="memory.addr1[11:0]" out_port="mem_2048x8_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[11:0]" output="mem_2048x8_dp.addr2">
+            <delay_constant max="132e-12" in_port="memory.addr2[11:0]" out_port="mem_2048x8_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[7:0]" output="mem_2048x8_dp.data1">
+            <delay_constant max="132e-12" in_port="memory.data[7:0]" out_port="mem_2048x8_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[15:8]" output="mem_2048x8_dp.data2">
+            <delay_constant max="132e-12" in_port="memory.data[15:8]" out_port="mem_2048x8_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_2048x8_dp.we1">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_2048x8_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_2048x8_dp.we2">
+            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_2048x8_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_2048x8_dp.out1" output="memory.out[7:0]">
+            <delay_constant max="40e-12" in_port="mem_2048x8_dp.out1" out_port="memory.out[7:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_2048x8_dp.out2" output="memory.out[15:8]">
+            <delay_constant max="40e-12" in_port="mem_2048x8_dp.out2" out_port="memory.out[15:8]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_2048x8_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_8192x4_dp">
+        <pb_type name="mem_8192x4_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="13" port_class="address1"/>
+          <input name="addr2" num_pins="13" port_class="address2"/>
+          <input name="data1" num_pins="4" port_class="data_in1"/>
+          <input name="data2" num_pins="4" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="4" port_class="data_out1"/>
+          <output name="out2" num_pins="4" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_8192x4_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_8192x4_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[12:0]" output="mem_8192x4_dp.addr1">
+            <delay_constant max="132e-12" in_port="memory.addr1[12:0]" out_port="mem_8192x4_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[12:0]" output="mem_8192x4_dp.addr2">
+            <delay_constant max="132e-12" in_port="memory.addr2[12:0]" out_port="mem_8192x4_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[3:0]" output="mem_8192x4_dp.data1">
+            <delay_constant max="132e-12" in_port="memory.data[3:0]" out_port="mem_8192x4_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[7:4]" output="mem_8192x4_dp.data2">
+            <delay_constant max="132e-12" in_port="memory.data[7:4]" out_port="mem_8192x4_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_8192x4_dp.we1">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_8192x4_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_8192x4_dp.we2">
+            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_8192x4_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_8192x4_dp.out1" output="memory.out[3:0]">
+            <delay_constant max="40e-12" in_port="mem_8192x4_dp.out1" out_port="memory.out[3:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_8192x4_dp.out2" output="memory.out[7:4]">
+            <delay_constant max="40e-12" in_port="mem_8192x4_dp.out2" out_port="memory.out[7:4]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_8192x4_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_16384x2_dp">
+        <pb_type name="mem_16384x2_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="14" port_class="address1"/>
+          <input name="addr2" num_pins="14" port_class="address2"/>
+          <input name="data1" num_pins="2" port_class="data_in1"/>
+          <input name="data2" num_pins="2" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="2" port_class="data_out1"/>
+          <output name="out2" num_pins="2" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_16384x2_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_16384x2_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[13:0]" output="mem_16384x2_dp.addr1">
+            <delay_constant max="132e-12" in_port="memory.addr1[13:0]" out_port="mem_16384x2_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[13:0]" output="mem_16384x2_dp.addr2">
+            <delay_constant max="132e-12" in_port="memory.addr2[13:0]" out_port="mem_16384x2_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[1:0]" output="mem_16384x2_dp.data1">
+            <delay_constant max="132e-12" in_port="memory.data[1:0]" out_port="mem_16384x2_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[3:2]" output="mem_16384x2_dp.data2">
+            <delay_constant max="132e-12" in_port="memory.data[3:2]" out_port="mem_16384x2_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_16384x2_dp.we1">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_16384x2_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_16384x2_dp.we2">
+            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_16384x2_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_16384x2_dp.out1" output="memory.out[1:0]">
+            <delay_constant max="40e-12" in_port="mem_16384x2_dp.out1" out_port="memory.out[1:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_16384x2_dp.out2" output="memory.out[3:2]">
+            <delay_constant max="40e-12" in_port="mem_16384x2_dp.out2" out_port="memory.out[3:2]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_16384x2_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_32768x1_dp">
+        <pb_type name="mem_32768x1_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="15" port_class="address1"/>
+          <input name="addr2" num_pins="15" port_class="address2"/>
+          <input name="data1" num_pins="1" port_class="data_in1"/>
+          <input name="data2" num_pins="1" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="1" port_class="data_out1"/>
+          <output name="out2" num_pins="1" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_32768x1_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_32768x1_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[14:0]" output="mem_32768x1_dp.addr1">
+            <delay_constant max="132e-12" in_port="memory.addr1[14:0]" out_port="mem_32768x1_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[14:0]" output="mem_32768x1_dp.addr2">
+            <delay_constant max="132e-12" in_port="memory.addr2[14:0]" out_port="mem_32768x1_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[0:0]" output="mem_32768x1_dp.data1">
+            <delay_constant max="132e-12" in_port="memory.data[0:0]" out_port="mem_32768x1_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[1:1]" output="mem_32768x1_dp.data2">
+            <delay_constant max="132e-12" in_port="memory.data[1:1]" out_port="mem_32768x1_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_32768x1_dp.we1">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_32768x1_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_32768x1_dp.we2">
+            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_32768x1_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_32768x1_dp.out1" output="memory.out[0:0]">
+            <delay_constant max="40e-12" in_port="mem_32768x1_dp.out1" out_port="memory.out[0:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_32768x1_dp.out2" output="memory.out[1:1]">
+            <delay_constant max="40e-12" in_port="mem_32768x1_dp.out2" out_port="memory.out[1:1]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_32768x1_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this memory block every 8 columns from (and including) the second column -->
+      <power method="sum-of-children"/>
+    </pb_type>
+    <!-- Define fracturable memory end -->
+  </complexblocklist>
+  <power>
+    <local_interconnect C_wire="2.5e-10"/>
+    <mux_transistor_size mux_transistor_size="3"/>
+    <FF_size FF_size="4"/>
+    <LUT_transistor_size LUT_transistor_size="4"/>
+  </power>
+  <clocks>
+    <clock buffer_size="auto" C_wire="2.5e-10"/>
+  </clocks>
+</architecture>
diff --git a/openfpga/test_blif/riscv_core_lut6.blif b/openfpga/test_blif/riscv_core_lut6.blif
new file mode 100644
index 000000000..a313bebc1
--- /dev/null
+++ b/openfpga/test_blif/riscv_core_lut6.blif
@@ -0,0 +1,19187 @@
+# Generated by Yosys 0.8+599 (git sha1 463f710, gcc 4.8.5 -fPIC -Os)
+
+.model riscv_core
+.inputs clock reset bus_read_data[0] bus_read_data[1] bus_read_data[2] bus_read_data[3] bus_read_data[4] bus_read_data[5] bus_read_data[6] bus_read_data[7] bus_read_data[8] bus_read_data[9] bus_read_data[10] bus_read_data[11] bus_read_data[12] bus_read_data[13] bus_read_data[14] bus_read_data[15] bus_read_data[16] bus_read_data[17] bus_read_data[18] bus_read_data[19] bus_read_data[20] bus_read_data[21] bus_read_data[22] bus_read_data[23] bus_read_data[24] bus_read_data[25] bus_read_data[26] bus_read_data[27] bus_read_data[28] bus_read_data[29] bus_read_data[30] bus_read_data[31] inst[0] inst[1] inst[2] inst[3] inst[4] inst[5] inst[6] inst[7] inst[8] inst[9] inst[10] inst[11] inst[12] inst[13] inst[14] inst[15] inst[16] inst[17] inst[18] inst[19] inst[20] inst[21] inst[22] inst[23] inst[24] inst[25] inst[26] inst[27] inst[28] inst[29] inst[30] inst[31] rs1_data[0] rs1_data[1] rs1_data[2] rs1_data[3] rs1_data[4] rs1_data[5] rs1_data[6] rs1_data[7] rs1_data[8] rs1_data[9] rs1_data[10] rs1_data[11] rs1_data[12] rs1_data[13] rs1_data[14] rs1_data[15] rs1_data[16] rs1_data[17] rs1_data[18] rs1_data[19] rs1_data[20] rs1_data[21] rs1_data[22] rs1_data[23] rs1_data[24] rs1_data[25] rs1_data[26] rs1_data[27] rs1_data[28] rs1_data[29] rs1_data[30] rs1_data[31] rs2_data[0] rs2_data[1] rs2_data[2] rs2_data[3] rs2_data[4] rs2_data[5] rs2_data[6] rs2_data[7] rs2_data[8] rs2_data[9] rs2_data[10] rs2_data[11] rs2_data[12] rs2_data[13] rs2_data[14] rs2_data[15] rs2_data[16] rs2_data[17] rs2_data[18] rs2_data[19] rs2_data[20] rs2_data[21] rs2_data[22] rs2_data[23] rs2_data[24] rs2_data[25] rs2_data[26] rs2_data[27] rs2_data[28] rs2_data[29] rs2_data[30] rs2_data[31]
+.outputs bus_address[0] bus_address[1] bus_address[2] bus_address[3] bus_address[4] bus_address[5] bus_address[6] bus_address[7] bus_address[8] bus_address[9] bus_address[10] bus_address[11] bus_address[12] bus_address[13] bus_address[14] bus_address[15] bus_address[16] bus_address[17] bus_address[18] bus_address[19] bus_address[20] bus_address[21] bus_address[22] bus_address[23] bus_address[24] bus_address[25] bus_address[26] bus_address[27] bus_address[28] bus_address[29] bus_address[30] bus_address[31] bus_write_data[0] bus_write_data[1] bus_write_data[2] bus_write_data[3] bus_write_data[4] bus_write_data[5] bus_write_data[6] bus_write_data[7] bus_write_data[8] bus_write_data[9] bus_write_data[10] bus_write_data[11] bus_write_data[12] bus_write_data[13] bus_write_data[14] bus_write_data[15] bus_write_data[16] bus_write_data[17] bus_write_data[18] bus_write_data[19] bus_write_data[20] bus_write_data[21] bus_write_data[22] bus_write_data[23] bus_write_data[24] bus_write_data[25] bus_write_data[26] bus_write_data[27] bus_write_data[28] bus_write_data[29] bus_write_data[30] bus_write_data[31] bus_byte_enable[0] bus_byte_enable[1] bus_byte_enable[2] bus_byte_enable[3] bus_read_enable bus_write_enable pc[0] pc[1] pc[2] pc[3] pc[4] pc[5] pc[6] pc[7] pc[8] pc[9] pc[10] pc[11] pc[12] pc[13] pc[14] pc[15] pc[16] pc[17] pc[18] pc[19] pc[20] pc[21] pc[22] pc[23] pc[24] pc[25] pc[26] pc[27] pc[28] pc[29] pc[30] pc[31] regfile_write_enable rd_address[0] rd_address[1] rd_address[2] rd_address[3] rd_address[4] rs1_address[0] rs1_address[1] rs1_address[2] rs1_address[3] rs1_address[4] rs2_address[0] rs2_address[1] rs2_address[2] rs2_address[3] rs2_address[4] rd_data[0] rd_data[1] rd_data[2] rd_data[3] rd_data[4] rd_data[5] rd_data[6] rd_data[7] rd_data[8] rd_data[9] rd_data[10] rd_data[11] rd_data[12] rd_data[13] rd_data[14] rd_data[15] rd_data[16] rd_data[17] rd_data[18] rd_data[19] rd_data[20] rd_data[21] rd_data[22] rd_data[23] rd_data[24] rd_data[25] rd_data[26] rd_data[27] rd_data[28] rd_data[29] rd_data[30] rd_data[31]
+.names $false
+.names $true
+1
+.names $undef
+.names $abc$8517$new_n299_ $abc$8517$new_n303_ inst[2] regfile_write_enable
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n302_ $abc$8517$new_n301_ $abc$8517$new_n300_ $abc$8517$new_n299_
+000 1
+.names inst[1] inst[0] inst[2] inst[4] inst[3] inst[6] $abc$8517$new_n300_
+111100 1
+.names inst[1] inst[0] inst[4] inst[2] inst[3] inst[6] $abc$8517$new_n301_
+111000 1
+.names inst[1] inst[0] inst[2] inst[6] inst[5] inst[4] $abc$8517$new_n302_
+111110 1
+.names inst[1] inst[0] inst[3] inst[6] inst[5] inst[4] $abc$8517$new_n303_
+110000 1
+.names $abc$8517$new_n1349_ $abc$8517$new_n1352_ $abc$8517$new_n466_ $abc$8517$new_n493_ $abc$8517$new_n1344_ bus_address[0]
+00000 1
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+.names $abc$8517$new_n307_ $abc$8517$new_n374_ $abc$8517$new_n407_ $abc$8517$new_n404_ $abc$8517$new_n409_ $abc$8517$new_n340_ $abc$8517$new_n306_
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+.names $abc$8517$new_n308_ $abc$8517$new_n322_ $abc$8517$new_n336_ $abc$8517$new_n307_
+110 1
+.names $abc$8517$new_n319_ $abc$8517$new_n316_ $abc$8517$new_n309_ $abc$8517$new_n308_
+000 1
+.names $abc$8517$new_n315_ $abc$8517$new_n310_ $abc$8517$new_n314_ inst[31] $abc$8517$new_n312_ rs2_data[19] $abc$8517$new_n309_
+000000 1
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+.names $abc$8517$new_n311_ inst[4] inst[6] $abc$8517$new_n302_ inst[5] inst[2] $abc$8517$new_n310_
+000000 1
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+.names inst[1] inst[0] inst[3] $abc$8517$new_n311_
+110 1
+.names $abc$8517$new_n313_ inst[3] inst[6] inst[5] inst[4] inst[2] $abc$8517$new_n312_
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+.names inst[1] inst[0] $abc$8517$new_n313_
+11 1
+.names inst[19] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n314_
+1011 1
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+1111 1
+.names rs1_data[19] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[19] $abc$8517$new_n315_
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+.names $abc$8517$new_n318_ $abc$8517$new_n310_ $abc$8517$new_n317_ inst[31] $abc$8517$new_n312_ rs2_data[18] $abc$8517$new_n316_
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+.names inst[18] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n317_
+1011 1
+1100 1
+1101 1
+1110 1
+1111 1
+.names rs1_data[18] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[18] $abc$8517$new_n318_
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+.names $abc$8517$new_n321_ $abc$8517$new_n310_ $abc$8517$new_n320_ inst[31] $abc$8517$new_n312_ rs2_data[17] $abc$8517$new_n319_
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+.names inst[17] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n320_
+1011 1
+1100 1
+1101 1
+1110 1
+1111 1
+.names rs1_data[17] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[17] $abc$8517$new_n321_
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+.names $abc$8517$new_n333_ $abc$8517$new_n330_ $abc$8517$new_n327_ $abc$8517$new_n323_ $abc$8517$new_n322_
+0000 1
+.names $abc$8517$new_n326_ $abc$8517$new_n310_ $abc$8517$new_n325_ inst[31] $abc$8517$new_n324_ rs2_data[23] $abc$8517$new_n323_
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+.names $abc$8517$new_n311_ inst[5] inst[2] inst[6] inst[4] $abc$8517$new_n302_ $abc$8517$new_n324_
+000000 1
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+.names inst[23] $abc$8517$new_n300_ $abc$8517$new_n325_
+11 1
+.names rs1_data[23] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[23] $abc$8517$new_n326_
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+.names $abc$8517$new_n329_ $abc$8517$new_n310_ $abc$8517$new_n328_ inst[31] $abc$8517$new_n324_ rs2_data[22] $abc$8517$new_n327_
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+.names inst[22] $abc$8517$new_n300_ $abc$8517$new_n328_
+11 1
+.names rs1_data[22] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n329_
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+.names $abc$8517$new_n332_ $abc$8517$new_n310_ $abc$8517$new_n331_ inst[31] $abc$8517$new_n324_ rs2_data[21] $abc$8517$new_n330_
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+.names inst[21] $abc$8517$new_n300_ $abc$8517$new_n331_
+11 1
+.names rs1_data[21] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[21] $abc$8517$new_n332_
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+.names $abc$8517$new_n335_ $abc$8517$new_n310_ $abc$8517$new_n334_ inst[31] $abc$8517$new_n324_ rs2_data[20] $abc$8517$new_n333_
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+.names inst[20] $abc$8517$new_n300_ $abc$8517$new_n334_
+11 1
+.names rs1_data[20] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[20] $abc$8517$new_n335_
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+.names $abc$8517$new_n339_ $abc$8517$new_n337_ $abc$8517$new_n336_
+01 1
+10 1
+.names $abc$8517$new_n310_ $abc$8517$new_n312_ rs2_data[16] inst[31] inst[16] $abc$8517$new_n337_
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+.names $abc$8517$new_n300_ $abc$8517$new_n302_ inst[3] $abc$8517$new_n338_
+000 1
+001 1
+010 1
+.names rs1_data[16] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[16] $abc$8517$new_n339_
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+.names $abc$8517$new_n1016_ bus_address[1] $abc$8517$new_n1015_
+11 1
+.names $abc$8517$new_n302_ inst[3] $abc$8517$new_n1016_
+10 1
+.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.program_counter.value[0] $abc$8517$new_n358_ $abc$8517$new_n357_ $abc$8517$new_n1013_ $abc$8517$new_n1017_
+00010 1
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+01000 1
+01011 1
+01101 1
+01111 1
+10000 1
+10001 1
+11001 1
+11010 1
+11100 1
+11110 1
+.names reset $abc$8517$new_n1019_ singlecycle_datapath.program_counter.value[2] $abc$8517$new_n999_ $abc$8517$new_n1020_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][2]
+000010 1
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+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[2] $abc$8517$new_n1019_
+11 1
+.names singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1022_ $abc$8517$new_n1021_ $abc$8517$new_n1020_
+001 1
+010 1
+100 1
+111 1
+.names inst[9] $abc$8517$new_n346_ inst[22] $abc$8517$new_n347_ $abc$8517$new_n1021_
+0000 1
+0001 1
+0011 1
+0100 1
+0101 1
+0111 1
+1100 1
+1101 1
+1111 1
+.names $abc$8517$new_n358_ $abc$8517$new_n357_ singlecycle_datapath.program_counter.value[1] $abc$8517$new_n354_ $abc$8517$new_n355_ singlecycle_datapath.program_counter.value[0] $abc$8517$new_n1022_
+000000 1
+000001 1
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+100000 1
+100001 1
+100010 1
+100100 1
+100110 1
+110000 1
+110001 1
+110010 1
+110100 1
+110110 1
+.names reset $abc$8517$new_n1024_ $abc$8517$new_n1028_ $abc$8517$new_n999_ $abc$8517$new_n1025_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][3]
+000010 1
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+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[3] $abc$8517$new_n1024_
+11 1
+.names singlecycle_datapath.program_counter.value[3] $abc$8517$new_n1027_ $abc$8517$new_n1026_ $abc$8517$new_n1025_
+001 1
+010 1
+100 1
+111 1
+.names $abc$8517$new_n1022_ singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1021_ $abc$8517$new_n1026_
+001 1
+100 1
+101 1
+111 1
+.names $abc$8517$new_n360_ $abc$8517$new_n347_ inst[23] $abc$8517$new_n1027_
+000 1
+010 1
+011 1
+.names singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1028_
+01 1
+10 1
+.names reset $abc$8517$new_n1030_ $abc$8517$new_n1033_ $abc$8517$new_n999_ $abc$8517$new_n1031_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][4]
+000010 1
+000110 1
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+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
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+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[4] $abc$8517$new_n1030_
+11 1
+.names singlecycle_datapath.program_counter.value[4] $abc$8517$new_n1032_ singlecycle_datapath.program_counter.value[3] $abc$8517$new_n1027_ $abc$8517$new_n1026_ $abc$8517$new_n1031_
+00001 1
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+01101 1
+01110 1
+10000 1
+10100 1
+10101 1
+10110 1
+11001 1
+11010 1
+11011 1
+11111 1
+.names inst[11] $abc$8517$new_n346_ inst[24] $abc$8517$new_n347_ $abc$8517$new_n1032_
+0000 1
+0001 1
+0011 1
+0100 1
+0101 1
+0111 1
+1100 1
+1101 1
+1111 1
+.names singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1033_
+011 1
+100 1
+101 1
+110 1
+.names reset $abc$8517$new_n1035_ $abc$8517$new_n1042_ $abc$8517$new_n999_ $abc$8517$new_n1036_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][5]
+000010 1
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+001110 1
+001111 1
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+010001 1
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+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[5] $abc$8517$new_n1035_
+11 1
+.names $abc$8517$new_n1041_ $abc$8517$new_n1037_ $abc$8517$new_n1036_
+00 1
+11 1
+.names $abc$8517$new_n1039_ $abc$8517$new_n1038_ $abc$8517$new_n1037_
+00 1
+.names singlecycle_datapath.program_counter.value[4] $abc$8517$new_n1032_ $abc$8517$new_n1038_
+10 1
+.names $abc$8517$new_n1040_ singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1022_ $abc$8517$new_n1021_ $abc$8517$new_n1027_ $abc$8517$new_n1039_
+100000 1
+101000 1
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+101100 1
+110000 1
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+110010 1
+110100 1
+110110 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+.names singlecycle_datapath.program_counter.value[4] $abc$8517$new_n347_ inst[24] inst[11] $abc$8517$new_n1040_
+0010 1
+0011 1
+0101 1
+0111 1
+1000 1
+1001 1
+1100 1
+1101 1
+1110 1
+.names singlecycle_datapath.program_counter.value[5] inst[25] $abc$8517$new_n324_ $abc$8517$new_n1041_
+010 1
+100 1
+101 1
+111 1
+.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1042_
+0111 1
+1000 1
+1001 1
+1010 1
+1011 1
+1100 1
+1101 1
+1110 1
+.names reset $abc$8517$new_n1044_ $abc$8517$new_n1048_ $abc$8517$new_n999_ $abc$8517$new_n1045_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][6]
+000010 1
+000110 1
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+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
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+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[6] $abc$8517$new_n1044_
+11 1
+.names $abc$8517$new_n1047_ $abc$8517$new_n1046_ $abc$8517$new_n1041_ $abc$8517$new_n1037_ $abc$8517$new_n1045_
+0010 1
+0100 1
+0101 1
+0110 1
+0111 1
+1000 1
+1001 1
+1011 1
+.names inst[25] singlecycle_datapath.program_counter.value[5] $abc$8517$new_n324_ $abc$8517$new_n1046_
+110 1
+.names singlecycle_datapath.program_counter.value[6] inst[26] $abc$8517$new_n324_ $abc$8517$new_n1047_
+010 1
+100 1
+101 1
+111 1
+.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1048_
+01111 1
+10000 1
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+10100 1
+10101 1
+10110 1
+10111 1
+11000 1
+11001 1
+11010 1
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+11100 1
+11101 1
+11110 1
+.names reset $abc$8517$new_n1050_ $abc$8517$new_n1054_ $abc$8517$new_n999_ $abc$8517$new_n1016_ bus_address[7] $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][7]
+000011 1
+000111 1
+001011 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1051_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1050_
+100001 1
+100011 1
+100101 1
+100111 1
+101001 1
+101011 1
+101101 1
+101111 1
+110000 1
+110001 1
+110010 1
+110011 1
+110101 1
+110110 1
+110111 1
+111001 1
+111011 1
+111100 1
+111101 1
+111111 1
+.names singlecycle_datapath.program_counter.value[7] $abc$8517$new_n699_ $abc$8517$new_n1052_ $abc$8517$new_n1051_
+000 1
+011 1
+101 1
+110 1
+.names $abc$8517$new_n1047_ $abc$8517$new_n1046_ singlecycle_datapath.program_counter.value[6] $abc$8517$new_n1041_ $abc$8517$new_n1038_ $abc$8517$new_n1039_ $abc$8517$new_n1052_
+000000 1
+000001 1
+000010 1
+000011 1
+000100 1
+000101 1
+000110 1
+000111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.program_counter.value[6] singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1054_
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
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+101101 1
+101110 1
+101111 1
+110000 1
+110001 1
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+110101 1
+110110 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+.names reset $abc$8517$new_n1056_ $abc$8517$new_n1060_ $abc$8517$new_n999_ $abc$8517$new_n1057_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][8]
+000010 1
+000110 1
+001010 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[8] $abc$8517$new_n1056_
+11 1
+.names singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1059_ $abc$8517$new_n1058_ $abc$8517$new_n1057_
+000 1
+011 1
+101 1
+110 1
+.names singlecycle_datapath.program_counter.value[7] $abc$8517$new_n699_ $abc$8517$new_n1052_ $abc$8517$new_n1058_
+000 1
+001 1
+011 1
+101 1
+.names inst[28] $abc$8517$new_n324_ $abc$8517$new_n1059_
+10 1
+.names singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1060_
+01 1
+10 1
+.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.program_counter.value[6] singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1061_
+111111 1
+.names reset $abc$8517$new_n1063_ $abc$8517$new_n1067_ $abc$8517$new_n999_ $abc$8517$new_n1064_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][9]
+000010 1
+000110 1
+001010 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[9] $abc$8517$new_n1063_
+11 1
+.names $abc$8517$new_n1066_ $abc$8517$new_n1065_ singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1059_ $abc$8517$new_n1058_ $abc$8517$new_n1064_
+00000 1
+00001 1
+00011 1
+00101 1
+01010 1
+01100 1
+01110 1
+01111 1
+10010 1
+10100 1
+10110 1
+10111 1
+11010 1
+11100 1
+11110 1
+11111 1
+.names inst[29] singlecycle_datapath.program_counter.value[9] $abc$8517$new_n324_ $abc$8517$new_n1065_
+110 1
+.names singlecycle_datapath.program_counter.value[9] $abc$8517$new_n324_ inst[29] $abc$8517$new_n1066_
+000 1
+010 1
+011 1
+.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1067_
+011 1
+100 1
+101 1
+110 1
+.names reset $abc$8517$new_n1069_ $abc$8517$new_n1073_ $abc$8517$new_n999_ $abc$8517$new_n1070_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][10]
+000010 1
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+001010 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
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+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[10] $abc$8517$new_n1069_
+11 1
+.names $abc$8517$new_n1072_ $abc$8517$new_n1066_ $abc$8517$new_n1071_ $abc$8517$new_n1070_
+000 1
+101 1
+110 1
+111 1
+.names $abc$8517$new_n1065_ singlecycle_datapath.program_counter.value[7] $abc$8517$new_n699_ singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1059_ $abc$8517$new_n1052_ $abc$8517$new_n1071_
+000000 1
+000001 1
+000010 1
+000011 1
+000100 1
+000101 1
+001000 1
+001001 1
+001011 1
+001101 1
+010000 1
+010001 1
+010011 1
+010101 1
+011000 1
+011001 1
+.names singlecycle_datapath.program_counter.value[10] inst[30] $abc$8517$new_n324_ $abc$8517$new_n1072_
+010 1
+100 1
+101 1
+111 1
+.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1073_
+0111 1
+1000 1
+1001 1
+1010 1
+1011 1
+1100 1
+1101 1
+1110 1
+.names reset $abc$8517$new_n1075_ $abc$8517$new_n1079_ $abc$8517$new_n999_ $abc$8517$new_n1016_ bus_address[11] $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][11]
+000011 1
+000111 1
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+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
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+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1076_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1075_
+000001 1
+000011 1
+000101 1
+000111 1
+001001 1
+001011 1
+001101 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010101 1
+010110 1
+010111 1
+011001 1
+011011 1
+011100 1
+011101 1
+011111 1
+.names singlecycle_datapath.program_counter.value[11] $abc$8517$new_n1077_ $abc$8517$new_n1078_ $abc$8517$new_n1072_ $abc$8517$new_n1066_ $abc$8517$new_n1071_ $abc$8517$new_n1076_
+000100 1
+001000 1
+001001 1
+001010 1
+001011 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010101 1
+010110 1
+010111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100101 1
+100110 1
+100111 1
+110100 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+111111 1
+.names $abc$8517$new_n390_ $abc$8517$new_n391_ $abc$8517$new_n389_ inst[31] $abc$8517$new_n1077_
+0000 1
+0010 1
+0011 1
+.names singlecycle_datapath.program_counter.value[10] inst[30] $abc$8517$new_n324_ $abc$8517$new_n1078_
+110 1
+.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1079_
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10110 1
+10111 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+.names reset $abc$8517$new_n1081_ $abc$8517$new_n1086_ $abc$8517$new_n999_ $abc$8517$new_n1082_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][12]
+000010 1
+000110 1
+001010 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[12] $abc$8517$new_n1081_
+11 1
+.names singlecycle_datapath.program_counter.value[12] $abc$8517$new_n1084_ $abc$8517$new_n1083_ $abc$8517$new_n1082_
+000 1
+011 1
+101 1
+110 1
+.names singlecycle_datapath.program_counter.value[11] $abc$8517$new_n1077_ $abc$8517$new_n1072_ $abc$8517$new_n1071_ $abc$8517$new_n1066_ $abc$8517$new_n1078_ $abc$8517$new_n1083_
+000001 1
+000011 1
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+000111 1
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+101111 1
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+111111 1
+.names $abc$8517$new_n1085_ $abc$8517$new_n338_ inst[12] $abc$8517$new_n1084_
+000 1
+010 1
+011 1
+.names inst[31] $abc$8517$new_n312_ $abc$8517$new_n1085_
+10 1
+.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.program_counter.value[11] singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1086_
+011111 1
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+110101 1
+110110 1
+110111 1
+111000 1
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+111010 1
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+111100 1
+111101 1
+111110 1
+.names reset $abc$8517$new_n1091_ $abc$8517$new_n1092_ $abc$8517$new_n999_ $abc$8517$new_n1088_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][13]
+000010 1
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+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1090_ $abc$8517$new_n1089_ $abc$8517$new_n1088_
+001 1
+010 1
+100 1
+111 1
+.names $abc$8517$new_n1084_ singlecycle_datapath.program_counter.value[12] $abc$8517$new_n1083_ $abc$8517$new_n1089_
+000 1
+100 1
+101 1
+110 1
+.names $abc$8517$new_n383_ $abc$8517$new_n1085_ $abc$8517$new_n1090_
+00 1
+.names $abc$8517$new_n1016_ bus_address[13] $abc$8517$new_n1091_
+11 1
+.names singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1092_
+01 1
+10 1
+.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.program_counter.value[11] singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1093_
+111111 1
+.names reset $abc$8517$new_n1095_ $abc$8517$new_n1098_ $abc$8517$new_n999_ $abc$8517$new_n1096_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][14]
+000010 1
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+011000 1
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+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[14] $abc$8517$new_n1095_
+11 1
+.names singlecycle_datapath.program_counter.value[14] $abc$8517$new_n1097_ singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1090_ $abc$8517$new_n1089_ $abc$8517$new_n1096_
+00001 1
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+10000 1
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+.names $abc$8517$new_n1085_ $abc$8517$new_n338_ inst[14] $abc$8517$new_n1097_
+000 1
+010 1
+011 1
+.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1098_
+011 1
+100 1
+101 1
+110 1
+.names reset $abc$8517$new_n1106_ $abc$8517$new_n1107_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1100_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][15]
+000000 1
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+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[15] $abc$8517$new_n1105_ $abc$8517$new_n1101_ $abc$8517$new_n1100_
+000 1
+011 1
+101 1
+110 1
+.names $abc$8517$new_n1104_ $abc$8517$new_n1102_ $abc$8517$new_n1101_
+00 1
+.names $abc$8517$new_n1103_ singlecycle_datapath.program_counter.value[12] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1084_ $abc$8517$new_n1090_ $abc$8517$new_n1083_ $abc$8517$new_n1102_
+100001 1
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+110000 1
+110001 1
+110101 1
+111000 1
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+111010 1
+111011 1
+111100 1
+111101 1
+111111 1
+.names singlecycle_datapath.program_counter.value[14] $abc$8517$new_n1097_ $abc$8517$new_n1103_
+00 1
+11 1
+.names singlecycle_datapath.program_counter.value[14] $abc$8517$new_n1097_ $abc$8517$new_n1104_
+10 1
+.names $abc$8517$new_n378_ $abc$8517$new_n1085_ $abc$8517$new_n1105_
+00 1
+.names $abc$8517$new_n1016_ bus_address[15] $abc$8517$new_n1106_
+11 1
+.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1107_
+0111 1
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+1001 1
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+1011 1
+1100 1
+1101 1
+1110 1
+.names reset $abc$8517$new_n1109_ $abc$8517$new_n1112_ $abc$8517$new_n999_ $abc$8517$new_n1110_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][16]
+000010 1
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+011000 1
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+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[16] $abc$8517$new_n1109_
+11 1
+.names singlecycle_datapath.program_counter.value[16] $abc$8517$new_n1111_ singlecycle_datapath.program_counter.value[15] $abc$8517$new_n1105_ $abc$8517$new_n1101_ $abc$8517$new_n1110_
+00001 1
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+.names $abc$8517$new_n1085_ $abc$8517$new_n338_ inst[16] $abc$8517$new_n1111_
+000 1
+010 1
+011 1
+.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1112_
+01111 1
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+10101 1
+10110 1
+10111 1
+11000 1
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+11010 1
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+11101 1
+11110 1
+.names reset $abc$8517$new_n1114_ $abc$8517$new_n1118_ $abc$8517$new_n999_ bus_address[17] $abc$8517$new_n1016_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][17]
+000011 1
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+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1115_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1114_
+000001 1
+000011 1
+000101 1
+000111 1
+001001 1
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+010000 1
+010001 1
+010010 1
+010011 1
+010101 1
+010110 1
+010111 1
+011001 1
+011011 1
+011100 1
+011101 1
+011111 1
+.names singlecycle_datapath.program_counter.value[17] $abc$8517$new_n1117_ $abc$8517$new_n1116_ $abc$8517$new_n1115_
+000 1
+011 1
+101 1
+110 1
+.names $abc$8517$new_n1104_ $abc$8517$new_n1102_ singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] $abc$8517$new_n1105_ $abc$8517$new_n1111_ $abc$8517$new_n1116_
+000000 1
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+110111 1
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+.names $abc$8517$new_n320_ $abc$8517$new_n1085_ $abc$8517$new_n1117_
+00 1
+.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1118_
+011111 1
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+110101 1
+110110 1
+110111 1
+111000 1
+111001 1
+111010 1
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+111100 1
+111101 1
+111110 1
+.names reset $abc$8517$new_n1123_ $abc$8517$new_n1124_ $abc$8517$new_n999_ $abc$8517$new_n1120_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][18]
+000010 1
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+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1122_ $abc$8517$new_n1121_ $abc$8517$new_n1120_
+000 1
+011 1
+101 1
+110 1
+.names singlecycle_datapath.program_counter.value[17] $abc$8517$new_n1117_ $abc$8517$new_n1116_ $abc$8517$new_n1121_
+000 1
+100 1
+101 1
+110 1
+.names $abc$8517$new_n317_ $abc$8517$new_n1085_ $abc$8517$new_n1122_
+00 1
+.names $abc$8517$new_n1016_ bus_address[18] $abc$8517$new_n1123_
+11 1
+.names singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1124_
+01 1
+10 1
+.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1125_
+111111 1
+.names reset $abc$8517$new_n1129_ $abc$8517$new_n1130_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1127_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][19]
+000000 1
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+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[19] $abc$8517$new_n1128_ singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1122_ $abc$8517$new_n1121_ $abc$8517$new_n1127_
+00001 1
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+10000 1
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+11101 1
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+.names $abc$8517$new_n314_ $abc$8517$new_n1085_ $abc$8517$new_n1128_
+00 1
+.names $abc$8517$new_n1016_ bus_address[19] $abc$8517$new_n1129_
+11 1
+.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1130_
+011 1
+100 1
+101 1
+110 1
+.names reset $abc$8517$new_n1132_ $abc$8517$new_n1138_ $abc$8517$new_n999_ $abc$8517$new_n1133_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][20]
+000010 1
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+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[20] $abc$8517$new_n1132_
+11 1
+.names singlecycle_datapath.program_counter.value[20] $abc$8517$new_n1137_ $abc$8517$new_n1136_ $abc$8517$new_n1134_ $abc$8517$new_n1133_
+0001 1
+0010 1
+0011 1
+0100 1
+1000 1
+1101 1
+1110 1
+1111 1
+.names $abc$8517$new_n1135_ $abc$8517$new_n1117_ singlecycle_datapath.program_counter.value[17] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1122_ $abc$8517$new_n1116_ $abc$8517$new_n1134_
+000001 1
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+010000 1
+010001 1
+010010 1
+010011 1
+010110 1
+010111 1
+011001 1
+011010 1
+011011 1
+011111 1
+.names singlecycle_datapath.program_counter.value[19] $abc$8517$new_n1128_ $abc$8517$new_n1135_
+10 1
+.names $abc$8517$new_n1128_ singlecycle_datapath.program_counter.value[19] $abc$8517$new_n1136_
+10 1
+.names $abc$8517$new_n334_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1137_
+000 1
+010 1
+011 1
+.names singlecycle_datapath.program_counter.value[20] singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1138_
+0111 1
+1000 1
+1001 1
+1010 1
+1011 1
+1100 1
+1101 1
+1110 1
+.names reset $abc$8517$new_n1140_ $abc$8517$new_n1143_ $abc$8517$new_n999_ $abc$8517$new_n1141_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][21]
+000000 1
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+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[21] $abc$8517$new_n1140_
+11 1
+.names singlecycle_datapath.program_counter.value[21] $abc$8517$new_n1142_ singlecycle_datapath.program_counter.value[20] $abc$8517$new_n1137_ $abc$8517$new_n1136_ $abc$8517$new_n1134_ $abc$8517$new_n1141_
+000000 1
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+111100 1
+.names $abc$8517$new_n331_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1142_
+000 1
+010 1
+011 1
+.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.program_counter.value[20] singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1143_
+01111 1
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+11000 1
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+.names $abc$8517$new_n999_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1148_ $abc$8517$new_n1145_ $abc$8517$new_n1146_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][22]
+000000 1
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+100000 1
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+110011 1
+110100 1
+110101 1
+110110 1
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+111110 1
+.names reset bus_address[22] $abc$8517$new_n1016_ $abc$8517$new_n1145_
+000 1
+001 1
+010 1
+.names singlecycle_datapath.program_counter.value[22] $abc$8517$new_n414_ $abc$8517$new_n1147_ $abc$8517$new_n1146_
+000 1
+011 1
+101 1
+110 1
+.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.program_counter.value[20] $abc$8517$new_n1136_ $abc$8517$new_n1134_ $abc$8517$new_n1137_ $abc$8517$new_n1142_ $abc$8517$new_n1147_
+000000 1
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+110100 1
+110101 1
+110110 1
+111000 1
+111001 1
+111010 1
+111100 1
+111101 1
+111110 1
+.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.program_counter.value[20] singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1148_
+11111 1
+.names reset $abc$8517$new_n1152_ $abc$8517$new_n1153_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1150_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][23]
+000000 1
+000100 1
+001000 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[23] $abc$8517$new_n427_ $abc$8517$new_n1151_ $abc$8517$new_n1150_
+000 1
+011 1
+101 1
+110 1
+.names $abc$8517$new_n414_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1147_ $abc$8517$new_n1151_
+000 1
+100 1
+101 1
+110 1
+.names $abc$8517$new_n1016_ bus_address[23] $abc$8517$new_n1152_
+11 1
+.names singlecycle_datapath.program_counter.value[23] $abc$8517$new_n1154_ $abc$8517$new_n1153_
+01 1
+10 1
+.names singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1148_ $abc$8517$new_n1154_
+11 1
+.names reset $abc$8517$new_n1158_ $abc$8517$new_n1159_ $abc$8517$new_n999_ $abc$8517$new_n1156_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][24]
+000010 1
+000110 1
+001010 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1157_ singlecycle_datapath.program_counter.value[23] $abc$8517$new_n427_ $abc$8517$new_n1151_ $abc$8517$new_n1156_
+00001 1
+00010 1
+00011 1
+00111 1
+01000 1
+01100 1
+01101 1
+01110 1
+10000 1
+10100 1
+10101 1
+10110 1
+11001 1
+11010 1
+11011 1
+11111 1
+.names $abc$8517$new_n458_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1157_
+000 1
+010 1
+011 1
+.names $abc$8517$new_n1016_ bus_address[24] $abc$8517$new_n1158_
+11 1
+.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1159_
+01 1
+10 1
+.names singlecycle_datapath.program_counter.value[23] $abc$8517$new_n1154_ $abc$8517$new_n1160_
+11 1
+.names reset $abc$8517$new_n1168_ $abc$8517$new_n1169_ $abc$8517$new_n999_ $abc$8517$new_n1162_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][25]
+000010 1
+000110 1
+001010 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[25] $abc$8517$new_n1167_ $abc$8517$new_n1163_ $abc$8517$new_n1162_
+001 1
+010 1
+100 1
+111 1
+.names $abc$8517$new_n1166_ $abc$8517$new_n1164_ $abc$8517$new_n1163_
+00 1
+.names $abc$8517$new_n1165_ singlecycle_datapath.program_counter.value[22] singlecycle_datapath.program_counter.value[23] $abc$8517$new_n414_ $abc$8517$new_n427_ $abc$8517$new_n1147_ $abc$8517$new_n1164_
+100001 1
+101000 1
+101001 1
+101011 1
+101100 1
+101101 1
+110000 1
+110001 1
+110101 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111111 1
+.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1157_ $abc$8517$new_n1165_
+00 1
+11 1
+.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1157_ $abc$8517$new_n1166_
+10 1
+.names $abc$8517$new_n456_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1167_
+000 1
+010 1
+011 1
+.names $abc$8517$new_n1016_ bus_address[25] $abc$8517$new_n1168_
+11 1
+.names singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1169_
+011 1
+100 1
+101 1
+110 1
+.names reset $abc$8517$new_n1173_ $abc$8517$new_n1174_ $abc$8517$new_n999_ $abc$8517$new_n1171_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][26]
+000010 1
+000110 1
+001010 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[26] $abc$8517$new_n1172_ singlecycle_datapath.program_counter.value[25] $abc$8517$new_n1167_ $abc$8517$new_n1163_ $abc$8517$new_n1171_
+00001 1
+00010 1
+00011 1
+00111 1
+01000 1
+01100 1
+01101 1
+01110 1
+10000 1
+10100 1
+10101 1
+10110 1
+11001 1
+11010 1
+11011 1
+11111 1
+.names $abc$8517$new_n448_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1172_
+000 1
+010 1
+011 1
+.names $abc$8517$new_n1016_ bus_address[26] $abc$8517$new_n1173_
+11 1
+.names singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1174_
+0111 1
+1000 1
+1001 1
+1010 1
+1011 1
+1100 1
+1101 1
+1110 1
+.names reset $abc$8517$new_n1176_ $abc$8517$new_n1180_ $abc$8517$new_n999_ $abc$8517$new_n1177_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][27]
+000000 1
+000100 1
+001000 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[27] $abc$8517$new_n1176_
+11 1
+.names singlecycle_datapath.program_counter.value[27] $abc$8517$new_n1179_ $abc$8517$new_n1178_ $abc$8517$new_n1177_
+000 1
+011 1
+101 1
+110 1
+.names $abc$8517$new_n1166_ $abc$8517$new_n1164_ singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] $abc$8517$new_n1167_ $abc$8517$new_n1172_ $abc$8517$new_n1178_
+000000 1
+000001 1
+000010 1
+000011 1
+000101 1
+000110 1
+000111 1
+001001 1
+001011 1
+001111 1
+010001 1
+010010 1
+010011 1
+010101 1
+010111 1
+011011 1
+100001 1
+100010 1
+100011 1
+100101 1
+100111 1
+101011 1
+110001 1
+110010 1
+110011 1
+110101 1
+110111 1
+111011 1
+.names $abc$8517$new_n446_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1179_
+000 1
+010 1
+011 1
+.names singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1180_
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10110 1
+10111 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+.names reset $abc$8517$new_n1182_ $abc$8517$new_n1185_ $abc$8517$new_n999_ bus_address[28] $abc$8517$new_n1016_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][28]
+000011 1
+000111 1
+001011 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1183_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1182_
+100001 1
+100011 1
+100101 1
+100111 1
+101001 1
+101011 1
+101101 1
+101111 1
+110000 1
+110001 1
+110010 1
+110011 1
+110101 1
+110110 1
+110111 1
+111001 1
+111011 1
+111100 1
+111101 1
+111111 1
+.names singlecycle_datapath.program_counter.value[28] $abc$8517$new_n1184_ singlecycle_datapath.program_counter.value[27] $abc$8517$new_n1179_ $abc$8517$new_n1178_ $abc$8517$new_n1183_
+00001 1
+00010 1
+00011 1
+00111 1
+01000 1
+01100 1
+01101 1
+01110 1
+10000 1
+10100 1
+10101 1
+10110 1
+11001 1
+11010 1
+11011 1
+11111 1
+.names $abc$8517$new_n439_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1184_
+000 1
+010 1
+011 1
+.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1185_
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+.names reset $abc$8517$new_n1190_ $abc$8517$new_n1191_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1187_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][29]
+000000 1
+000100 1
+001000 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1189_ $abc$8517$new_n1188_ $abc$8517$new_n1187_
+000 1
+011 1
+101 1
+110 1
+.names $abc$8517$new_n1179_ singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[28] $abc$8517$new_n1184_ $abc$8517$new_n1178_ $abc$8517$new_n1188_
+00001 1
+00010 1
+00011 1
+00111 1
+01010 1
+01011 1
+10000 1
+10001 1
+10010 1
+10011 1
+10110 1
+10111 1
+11001 1
+11010 1
+11011 1
+11111 1
+.names inst[31] $abc$8517$new_n324_ $abc$8517$new_n300_ inst[29] $abc$8517$new_n1189_
+0000 1
+0001 1
+0010 1
+0100 1
+0101 1
+0110 1
+1100 1
+1101 1
+1110 1
+.names $abc$8517$new_n1016_ bus_address[29] $abc$8517$new_n1190_
+11 1
+.names singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1192_ $abc$8517$new_n1191_
+01 1
+10 1
+.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1192_
+111111 1
+.names reset $abc$8517$new_n1194_ $abc$8517$new_n1197_ $abc$8517$new_n999_ $abc$8517$new_n1195_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][30]
+000010 1
+000110 1
+001010 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[30] $abc$8517$new_n1194_
+11 1
+.names singlecycle_datapath.program_counter.value[30] $abc$8517$new_n1196_ singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1189_ $abc$8517$new_n1188_ $abc$8517$new_n1195_
+00001 1
+00010 1
+00011 1
+00111 1
+01000 1
+01100 1
+01101 1
+01110 1
+10000 1
+10100 1
+10101 1
+10110 1
+11001 1
+11010 1
+11011 1
+11111 1
+.names inst[31] $abc$8517$new_n324_ $abc$8517$new_n300_ inst[30] $abc$8517$new_n1196_
+0000 1
+0001 1
+0010 1
+0100 1
+0101 1
+0110 1
+1100 1
+1101 1
+1110 1
+.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1192_ $abc$8517$new_n1197_
+011 1
+100 1
+101 1
+110 1
+.names reset $abc$8517$new_n999_ singlecycle_datapath.program_counter.value[31] $abc$8517$new_n1203_ $abc$8517$new_n1199_ $abc$8517$new_n1202_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][31]
+000001 1
+000010 1
+000011 1
+000101 1
+000110 1
+000111 1
+001001 1
+001010 1
+001011 1
+001101 1
+001110 1
+001111 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1200_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1199_
+000001 1
+000011 1
+000101 1
+000111 1
+001001 1
+001011 1
+001101 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010101 1
+010110 1
+010111 1
+011001 1
+011011 1
+011100 1
+011101 1
+011111 1
+.names $abc$8517$new_n1201_ $abc$8517$new_n1189_ singlecycle_datapath.program_counter.value[29] singlecycle_datapath.program_counter.value[30] $abc$8517$new_n1196_ $abc$8517$new_n1188_ $abc$8517$new_n1200_
+000001 1
+000010 1
+000011 1
+000111 1
+001010 1
+001011 1
+010000 1
+010001 1
+010010 1
+010011 1
+010110 1
+010111 1
+011001 1
+011010 1
+011011 1
+011111 1
+100000 1
+100100 1
+100101 1
+100110 1
+101000 1
+101001 1
+101100 1
+101101 1
+101110 1
+101111 1
+110100 1
+110101 1
+111000 1
+111100 1
+111101 1
+111110 1
+.names singlecycle_datapath.program_counter.value[31] $abc$8517$new_n494_ $abc$8517$new_n1201_
+00 1
+11 1
+.names $abc$8517$new_n1016_ bus_address[31] $abc$8517$new_n1202_
+11 1
+.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1192_ $abc$8517$new_n1203_
+111 1
+.names $abc$8517$new_n1005_ inst[13] inst[12] bus_byte_enable[0]
+100 1
+101 1
+110 1
+.names inst[12] bus_address[1] inst[13] bus_address[0] bus_byte_enable[1]
+0001 1
+0010 1
+0011 1
+1000 1
+1001 1
+.names inst[13] inst[12] bus_address[0] bus_address[1] bus_byte_enable[2]
+0001 1
+0101 1
+0110 1
+1000 1
+1001 1
+1010 1
+.names inst[12] bus_address[1] inst[13] bus_address[0] bus_byte_enable[3]
+0010 1
+0011 1
+0101 1
+0110 1
+0111 1
+1100 1
+1101 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1209_ bus_address[0] $abc$8517$new_n1210_ singlecycle_datapath.program_counter.value[0] $abc$8517$new_n302_ rd_data[0]
+000011 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001111 1
+010011 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110011 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111111 1
+.names bus_address[1] bus_address[0] bus_read_data[24] bus_read_data[8] bus_read_data[16] bus_read_data[0] $abc$8517$new_n1209_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
+100100 1
+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n301_ $abc$8517$new_n300_ inst[5] $abc$8517$new_n1210_
+000 1
+001 1
+011 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1212_ bus_address[1] $abc$8517$new_n1210_ singlecycle_datapath.program_counter.value[1] $abc$8517$new_n302_ rd_data[1]
+000011 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001111 1
+010011 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110011 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111111 1
+.names bus_address[1] bus_address[0] bus_read_data[25] bus_read_data[9] bus_read_data[17] bus_read_data[1] $abc$8517$new_n1212_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
+100100 1
+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1214_ bus_address[2] $abc$8517$new_n1210_ $abc$8517$new_n302_ singlecycle_datapath.program_counter.value[2] rd_data[2]
+000010 1
+000110 1
+001000 1
+001001 1
+001010 1
+001011 1
+001110 1
+010010 1
+010110 1
+011000 1
+011001 1
+011010 1
+011011 1
+011110 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110010 1
+110110 1
+111000 1
+111001 1
+111010 1
+111011 1
+111110 1
+.names bus_address[1] bus_address[0] bus_read_data[26] bus_read_data[10] bus_read_data[18] bus_read_data[2] $abc$8517$new_n1214_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
+100100 1
+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1216_ bus_address[3] $abc$8517$new_n1210_ $abc$8517$new_n1028_ $abc$8517$new_n302_ rd_data[3]
+000011 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001111 1
+010011 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110011 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111111 1
+.names bus_address[1] bus_address[0] bus_read_data[27] bus_read_data[11] bus_read_data[19] bus_read_data[3] $abc$8517$new_n1216_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
+100100 1
+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1218_ bus_address[4] $abc$8517$new_n1210_ $abc$8517$new_n1033_ $abc$8517$new_n302_ rd_data[4]
+000011 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001111 1
+010011 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110011 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111111 1
+.names bus_address[1] bus_address[0] bus_read_data[28] bus_read_data[12] bus_read_data[20] bus_read_data[4] $abc$8517$new_n1218_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
+100100 1
+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1220_ bus_address[5] $abc$8517$new_n1210_ $abc$8517$new_n1042_ $abc$8517$new_n302_ rd_data[5]
+000011 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001111 1
+010011 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110011 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111111 1
+.names bus_address[1] bus_address[0] bus_read_data[29] bus_read_data[13] bus_read_data[21] bus_read_data[5] $abc$8517$new_n1220_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
+100100 1
+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1222_ bus_address[6] $abc$8517$new_n1210_ $abc$8517$new_n1048_ $abc$8517$new_n302_ rd_data[6]
+000011 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001111 1
+010011 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110011 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111111 1
+.names bus_address[1] bus_address[0] bus_read_data[30] bus_read_data[14] bus_read_data[22] bus_read_data[6] $abc$8517$new_n1222_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
+100100 1
+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1224_ bus_address[7] $abc$8517$new_n1210_ $abc$8517$new_n1054_ $abc$8517$new_n302_ rd_data[7]
+000011 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001111 1
+010011 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110011 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111111 1
+.names bus_address[1] bus_address[0] bus_read_data[31] bus_read_data[15] bus_read_data[23] bus_read_data[7] $abc$8517$new_n1224_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
+100100 1
+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n1226_ $abc$8517$new_n1210_ bus_address[8] $abc$8517$new_n1060_ $abc$8517$new_n302_ rd_data[8]
+00011 1
+00100 1
+00101 1
+00110 1
+00111 1
+01011 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10110 1
+10111 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1228_ $abc$8517$new_n1227_ $abc$8517$new_n1226_
+10001 1
+10011 1
+10100 1
+10101 1
+10111 1
+11000 1
+11001 1
+11011 1
+11101 1
+11111 1
+.names inst[13] inst[12] inst[14] $abc$8517$new_n1224_ $abc$8517$new_n1227_
+0000 1
+1100 1
+.names bus_address[1] bus_address[0] bus_read_data[16] bus_read_data[24] bus_read_data[8] $abc$8517$new_n1228_
+00000 1
+00010 1
+00100 1
+00110 1
+01000 1
+01001 1
+01010 1
+01011 1
+10000 1
+10001 1
+10100 1
+10101 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n1230_ $abc$8517$new_n1210_ bus_address[9] $abc$8517$new_n1067_ $abc$8517$new_n302_ rd_data[9]
+00011 1
+00100 1
+00101 1
+00110 1
+00111 1
+01011 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10110 1
+10111 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1231_ $abc$8517$new_n1227_ $abc$8517$new_n1230_
+10001 1
+10011 1
+10100 1
+10101 1
+10111 1
+11000 1
+11001 1
+11011 1
+11101 1
+11111 1
+.names bus_address[1] bus_address[0] bus_read_data[17] bus_read_data[25] bus_read_data[9] $abc$8517$new_n1231_
+00000 1
+00010 1
+00100 1
+00110 1
+01000 1
+01001 1
+01010 1
+01011 1
+10000 1
+10001 1
+10100 1
+10101 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n1233_ $abc$8517$new_n1210_ bus_address[10] $abc$8517$new_n1073_ $abc$8517$new_n302_ rd_data[10]
+00011 1
+00100 1
+00101 1
+00110 1
+00111 1
+01011 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10110 1
+10111 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1234_ $abc$8517$new_n1227_ $abc$8517$new_n1233_
+10001 1
+10011 1
+10100 1
+10101 1
+10111 1
+11000 1
+11001 1
+11011 1
+11101 1
+11111 1
+.names bus_address[1] bus_address[0] bus_read_data[18] bus_read_data[26] bus_read_data[10] $abc$8517$new_n1234_
+00000 1
+00010 1
+00100 1
+00110 1
+01000 1
+01001 1
+01010 1
+01011 1
+10000 1
+10001 1
+10100 1
+10101 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n1236_ $abc$8517$new_n1210_ bus_address[11] $abc$8517$new_n1079_ $abc$8517$new_n302_ rd_data[11]
+00011 1
+00100 1
+00101 1
+00110 1
+00111 1
+01011 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10110 1
+10111 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1237_ $abc$8517$new_n1227_ $abc$8517$new_n1236_
+10001 1
+10011 1
+10100 1
+10101 1
+10111 1
+11000 1
+11001 1
+11011 1
+11101 1
+11111 1
+.names bus_address[1] bus_address[0] bus_read_data[19] bus_read_data[27] bus_read_data[11] $abc$8517$new_n1237_
+00000 1
+00010 1
+00100 1
+00110 1
+01000 1
+01001 1
+01010 1
+01011 1
+10000 1
+10001 1
+10100 1
+10101 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n1239_ $abc$8517$new_n302_ $abc$8517$new_n1086_ rd_data[12]
+000 1
+001 1
+010 1
+011 1
+111 1
+.names $abc$8517$new_n1241_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1240_ $abc$8517$new_n1239_
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100111 1
+101000 1
+101001 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110000 1
+110001 1
+110100 1
+110101 1
+111000 1
+111001 1
+111100 1
+111101 1
+.names bus_address[1] bus_address[0] bus_read_data[20] bus_read_data[28] bus_read_data[12] $abc$8517$new_n1240_
+00000 1
+00010 1
+00100 1
+00110 1
+01000 1
+01001 1
+01010 1
+01011 1
+10000 1
+10001 1
+10100 1
+10101 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n1210_ bus_address[12] $abc$8517$new_n300_ $abc$8517$new_n1084_ $abc$8517$new_n1241_
+0000 1
+0001 1
+0010 1
+0011 1
+1000 1
+1001 1
+1011 1
+1100 1
+1101 1
+1111 1
+.names $abc$8517$new_n1243_ bus_address[13] $abc$8517$new_n1210_ rd_data[13]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1245_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1244_ $abc$8517$new_n1243_
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100111 1
+101000 1
+101001 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110000 1
+110001 1
+110100 1
+110101 1
+111000 1
+111001 1
+111100 1
+111101 1
+.names bus_address[1] bus_address[0] bus_read_data[21] bus_read_data[29] bus_read_data[13] $abc$8517$new_n1244_
+00000 1
+00010 1
+00100 1
+00110 1
+01000 1
+01001 1
+01010 1
+01011 1
+10000 1
+10001 1
+10100 1
+10101 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n1092_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1090_ $abc$8517$new_n1245_
+00000 1
+00001 1
+00010 1
+00011 1
+00100 1
+00101 1
+00111 1
+01000 1
+01001 1
+01010 1
+01011 1
+01100 1
+01101 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10111 1
+.names $abc$8517$new_n1247_ bus_address[14] $abc$8517$new_n1210_ rd_data[14]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1249_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1248_ $abc$8517$new_n1247_
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100111 1
+101000 1
+101001 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110000 1
+110001 1
+110100 1
+110101 1
+111000 1
+111001 1
+111100 1
+111101 1
+.names bus_address[1] bus_address[0] bus_read_data[22] bus_read_data[30] bus_read_data[14] $abc$8517$new_n1248_
+00000 1
+00010 1
+00100 1
+00110 1
+01000 1
+01001 1
+01010 1
+01011 1
+10000 1
+10001 1
+10100 1
+10101 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n1098_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1097_ $abc$8517$new_n1249_
+00000 1
+00001 1
+00010 1
+00011 1
+00100 1
+00101 1
+00111 1
+01000 1
+01001 1
+01010 1
+01011 1
+01100 1
+01101 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10111 1
+.names $abc$8517$new_n1251_ bus_address[15] $abc$8517$new_n1210_ rd_data[15]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1253_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1252_ $abc$8517$new_n1251_
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100111 1
+101000 1
+101001 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110000 1
+110001 1
+110100 1
+110101 1
+111000 1
+111001 1
+111100 1
+111101 1
+.names bus_address[1] bus_address[0] bus_read_data[23] bus_read_data[31] bus_read_data[15] $abc$8517$new_n1252_
+00000 1
+00010 1
+00100 1
+00110 1
+01000 1
+01001 1
+01010 1
+01011 1
+10000 1
+10001 1
+10100 1
+10101 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n1107_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1105_ $abc$8517$new_n1253_
+00000 1
+00001 1
+00010 1
+00011 1
+00100 1
+00101 1
+00111 1
+01000 1
+01001 1
+01010 1
+01011 1
+01100 1
+01101 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10111 1
+.names $abc$8517$new_n1255_ bus_address[16] $abc$8517$new_n1210_ rd_data[16]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1256_ $abc$8517$new_n302_ $abc$8517$new_n1112_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1111_ $abc$8517$new_n1255_
+000000 1
+000001 1
+000010 1
+000011 1
+000100 1
+000101 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001100 1
+001101 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[24] bus_read_data[16] $abc$8517$new_n1256_
+100000 1
+100001 1
+100010 1
+100011 1
+101000 1
+101001 1
+101010 1
+101011 1
+110000 1
+110001 1
+110010 1
+110011 1
+110101 1
+110111 1
+111000 1
+111001 1
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+.names inst[12] inst[13] inst[14] $abc$8517$new_n1224_ $abc$8517$new_n1252_ $abc$8517$new_n1257_
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+.names inst[13] inst[12] bus_address[1] $abc$8517$new_n1258_
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+.names $abc$8517$new_n1260_ $abc$8517$new_n302_ $abc$8517$new_n1118_ rd_data[17]
+000 1
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+.names $abc$8517$new_n1261_ bus_address[17] $abc$8517$new_n1210_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1117_ $abc$8517$new_n1260_
+000000 1
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+.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[25] bus_read_data[17] $abc$8517$new_n1261_
+100000 1
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+.names $abc$8517$new_n1263_ bus_address[18] $abc$8517$new_n1210_ rd_data[18]
+000 1
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+.names $abc$8517$new_n1264_ $abc$8517$new_n302_ $abc$8517$new_n1124_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1122_ $abc$8517$new_n1263_
+000000 1
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+.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[26] bus_read_data[18] $abc$8517$new_n1264_
+100000 1
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+.names $abc$8517$new_n1266_ bus_address[19] $abc$8517$new_n1210_ rd_data[19]
+000 1
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+.names $abc$8517$new_n1267_ $abc$8517$new_n302_ $abc$8517$new_n1130_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1128_ $abc$8517$new_n1266_
+000000 1
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+.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[27] bus_read_data[19] $abc$8517$new_n1267_
+100000 1
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+.names $abc$8517$new_n1269_ bus_address[20] $abc$8517$new_n1210_ rd_data[20]
+000 1
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+.names $abc$8517$new_n1270_ $abc$8517$new_n302_ $abc$8517$new_n1138_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1137_ $abc$8517$new_n1269_
+000000 1
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+.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[28] bus_read_data[20] $abc$8517$new_n1270_
+100000 1
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+000 1
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+.names $abc$8517$new_n1273_ $abc$8517$new_n302_ $abc$8517$new_n1143_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1142_ $abc$8517$new_n1272_
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+.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[29] bus_read_data[21] $abc$8517$new_n1273_
+100000 1
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+0000 1
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+.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[30] bus_read_data[22] $abc$8517$new_n1275_
+100000 1
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+.names $abc$8517$new_n302_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1148_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n414_ $abc$8517$new_n1276_
+000000 1
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+.names $abc$8517$new_n1278_ bus_address[23] $abc$8517$new_n1210_ rd_data[23]
+000 1
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+.names $abc$8517$new_n1279_ $abc$8517$new_n302_ $abc$8517$new_n1153_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n427_ $abc$8517$new_n1278_
+000000 1
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+100000 1
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+000 1
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+.names $abc$8517$new_n1283_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[24] $abc$8517$new_n1281_
+10000 1
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+10 1
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+000 1
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+.names $abc$8517$new_n1286_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[25] $abc$8517$new_n1285_
+10000 1
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+.names $abc$8517$new_n1169_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1167_ $abc$8517$new_n1286_
+00000 1
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+000 1
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+.names $abc$8517$new_n1289_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[26] $abc$8517$new_n1288_
+10000 1
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+00000 1
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+.names $abc$8517$new_n1291_ bus_address[27] $abc$8517$new_n1210_ rd_data[27]
+000 1
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+.names $abc$8517$new_n1292_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[27] $abc$8517$new_n1291_
+10000 1
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+00000 1
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+000 1
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+.names $abc$8517$new_n1295_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[28] $abc$8517$new_n1294_
+10000 1
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+00000 1
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+000 1
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+.names $abc$8517$new_n1298_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[29] $abc$8517$new_n1297_
+10000 1
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+.names $abc$8517$new_n1191_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1189_ $abc$8517$new_n1298_
+00000 1
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+.names $abc$8517$new_n1300_ bus_address[30] $abc$8517$new_n1210_ rd_data[30]
+000 1
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+.names $abc$8517$new_n1301_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[30] $abc$8517$new_n1300_
+10000 1
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+.names $abc$8517$new_n1197_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1196_ $abc$8517$new_n1301_
+00000 1
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+10000 1
+10001 1
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+10100 1
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+10111 1
+.names $abc$8517$new_n1304_ $abc$8517$new_n1303_ bus_address[31] $abc$8517$new_n1210_ rd_data[31]
+0000 1
+0001 1
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+0011 1
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+1111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1257_ bus_read_data[31] $abc$8517$new_n1282_ $abc$8517$new_n1303_
+1000 1
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+1011 1
+1111 1
+.names $abc$8517$new_n302_ singlecycle_datapath.program_counter.value[31] $abc$8517$new_n1203_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n494_ $abc$8517$new_n1304_
+000000 1
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+.names $abc$8517$new_n299_ $abc$8517$new_n1009_ $abc$8517$new_n348_ $abc$8517$new_n1307_ $abc$8517$new_n1306_ inst[3] bus_write_enable
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+101000 1
+101001 1
+101010 1
+101011 1
+.names inst[2] $abc$8517$new_n313_ $abc$8517$new_n1306_
+11 1
+.names inst[6] inst[5] inst[4] $abc$8517$new_n1307_
+000 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1306_ $abc$8517$new_n346_ $abc$8517$new_n1310_ bus_read_enable
+1010 1
+1011 1
+1100 1
+1110 1
+.names inst[3] $abc$8517$new_n1307_ $abc$8517$new_n1310_
+11 1
+.names rs2_data[0] $abc$8517$new_n1005_ bus_write_data[0]
+11 1
+.names rs2_data[1] $abc$8517$new_n1005_ bus_write_data[1]
+11 1
+.names rs2_data[2] $abc$8517$new_n1005_ bus_write_data[2]
+11 1
+.names rs2_data[3] $abc$8517$new_n1005_ bus_write_data[3]
+11 1
+.names rs2_data[4] $abc$8517$new_n1005_ bus_write_data[4]
+11 1
+.names rs2_data[5] $abc$8517$new_n1005_ bus_write_data[5]
+11 1
+.names rs2_data[6] $abc$8517$new_n1005_ bus_write_data[6]
+11 1
+.names rs2_data[7] $abc$8517$new_n1005_ bus_write_data[7]
+11 1
+.names bus_address[0] bus_address[1] rs2_data[0] rs2_data[8] bus_write_data[8]
+0001 1
+0011 1
+1010 1
+1011 1
+.names bus_address[0] bus_address[1] rs2_data[1] rs2_data[9] bus_write_data[9]
+0001 1
+0011 1
+1010 1
+1011 1
+.names bus_address[0] bus_address[1] rs2_data[2] rs2_data[10] bus_write_data[10]
+0001 1
+0011 1
+1010 1
+1011 1
+.names bus_address[0] bus_address[1] rs2_data[3] rs2_data[11] bus_write_data[11]
+0001 1
+0011 1
+1010 1
+1011 1
+.names bus_address[0] bus_address[1] rs2_data[4] rs2_data[12] bus_write_data[12]
+0001 1
+0011 1
+1010 1
+1011 1
+.names bus_address[0] bus_address[1] rs2_data[5] rs2_data[13] bus_write_data[13]
+0001 1
+0011 1
+1010 1
+1011 1
+.names bus_address[0] bus_address[1] rs2_data[6] rs2_data[14] bus_write_data[14]
+0001 1
+0011 1
+1010 1
+1011 1
+.names bus_address[0] bus_address[1] rs2_data[7] rs2_data[15] bus_write_data[15]
+0001 1
+0011 1
+1010 1
+1011 1
+.names bus_address[1] bus_address[0] rs2_data[8] rs2_data[0] rs2_data[16] bus_write_data[16]
+00001 1
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+01101 1
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+01111 1
+10010 1
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+10110 1
+10111 1
+.names bus_address[1] bus_address[0] rs2_data[9] rs2_data[1] rs2_data[17] bus_write_data[17]
+00001 1
+00011 1
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+00111 1
+01100 1
+01101 1
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+.names bus_address[1] bus_address[0] rs2_data[10] rs2_data[2] rs2_data[18] bus_write_data[18]
+00001 1
+00011 1
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+00111 1
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+01101 1
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+.names bus_address[1] bus_address[0] rs2_data[11] rs2_data[3] rs2_data[19] bus_write_data[19]
+00001 1
+00011 1
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+01101 1
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+.names bus_address[1] bus_address[0] rs2_data[12] rs2_data[4] rs2_data[20] bus_write_data[20]
+00001 1
+00011 1
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+.names bus_address[1] bus_address[0] rs2_data[13] rs2_data[5] rs2_data[21] bus_write_data[21]
+00001 1
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+.names bus_address[1] bus_address[0] rs2_data[14] rs2_data[6] rs2_data[22] bus_write_data[22]
+00001 1
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+.names bus_address[1] bus_address[0] rs2_data[15] rs2_data[7] rs2_data[23] bus_write_data[23]
+00001 1
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+.names bus_address[1] bus_address[0] rs2_data[0] rs2_data[16] rs2_data[8] rs2_data[24] bus_write_data[24]
+000001 1
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+.names bus_address[1] bus_address[0] rs2_data[1] rs2_data[17] rs2_data[9] rs2_data[25] bus_write_data[25]
+000001 1
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+.names bus_address[1] bus_address[0] rs2_data[2] rs2_data[18] rs2_data[10] rs2_data[26] bus_write_data[26]
+000001 1
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+.names bus_address[1] bus_address[0] rs2_data[3] rs2_data[19] rs2_data[11] rs2_data[27] bus_write_data[27]
+000001 1
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+.names bus_address[1] bus_address[0] rs2_data[4] rs2_data[20] rs2_data[12] rs2_data[28] bus_write_data[28]
+000001 1
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+.names bus_address[1] bus_address[0] rs2_data[5] rs2_data[21] rs2_data[13] rs2_data[29] bus_write_data[29]
+000001 1
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+.names bus_address[1] bus_address[0] rs2_data[6] rs2_data[22] rs2_data[14] rs2_data[30] bus_write_data[30]
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+.names bus_address[1] bus_address[0] rs2_data[7] rs2_data[23] rs2_data[15] rs2_data[31] bus_write_data[31]
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+.names $abc$8517$new_n462_ $abc$8517$new_n444_ $abc$8517$new_n306_ $abc$8517$new_n411_ $abc$8517$new_n454_ $abc$8517$new_n451_ $abc$8517$new_n1343_
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+.names $abc$8517$new_n433_ $abc$8517$new_n436_ $abc$8517$new_n432_ $abc$8517$new_n431_ $abc$8517$new_n442_ $abc$8517$new_n1343_ $abc$8517$new_n1344_
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+.names $abc$8517$new_n310_ rs2_data[19] $abc$8517$new_n314_ inst[31] $abc$8517$new_n312_ $abc$8517$new_n1345_
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+.names $abc$8517$new_n318_ $abc$8517$new_n315_ $abc$8517$new_n423_ $abc$8517$new_n1345_ $abc$8517$new_n335_ $abc$8517$new_n418_ $abc$8517$new_n1346_
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+.names $abc$8517$new_n433_ $abc$8517$new_n461_ $abc$8517$new_n432_ $abc$8517$new_n431_ $abc$8517$new_n411_ $abc$8517$new_n306_ $abc$8517$new_n1348_
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+.names $abc$8517$new_n495_ $abc$8517$new_n1348_ $abc$8517$new_n493_ $abc$8517$new_n492_ $abc$8517$new_n1349_
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+.names $abc$8517$new_n575_ $abc$8517$new_n578_ $abc$8517$new_n345_ $abc$8517$new_n554_ $abc$8517$new_n1353_ $abc$8517$new_n549_ bus_address[1]
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+.names $abc$8517$new_n1359_ $abc$8517$new_n653_ $abc$8517$new_n647_ $abc$8517$new_n646_ $abc$8517$new_n549_ $abc$8517$new_n657_ bus_address[5]
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+.names $abc$8517$new_n543_ $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n682_ $abc$8517$new_n681_ $abc$8517$new_n680_ $abc$8517$new_n1361_
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+.names $abc$8517$new_n1361_ $abc$8517$new_n665_ $abc$8517$new_n368_ $abc$8517$new_n549_ $abc$8517$new_n1365_ $abc$8517$new_n1367_ $abc$8517$new_n1362_
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+.names $abc$8517$new_n663_ $abc$8517$new_n548_ $abc$8517$new_n664_ $abc$8517$new_n546_ $abc$8517$new_n662_ $abc$8517$new_n1362_ bus_address[6]
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+.names $abc$8517$new_n362_ $abc$8517$new_n356_ $abc$8517$new_n517_ $abc$8517$new_n516_ $abc$8517$new_n507_ $abc$8517$new_n506_ $abc$8517$new_n1364_
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+.names $abc$8517$new_n1364_ $abc$8517$new_n356_ $abc$8517$new_n505_ $abc$8517$new_n504_ $abc$8517$new_n510_ $abc$8517$new_n509_ $abc$8517$new_n1365_
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+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][1] singlecycle_datapath.program_counter.value[1] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][2] singlecycle_datapath.program_counter.value[2] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][3] singlecycle_datapath.program_counter.value[3] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][4] singlecycle_datapath.program_counter.value[4] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][5] singlecycle_datapath.program_counter.value[5] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][6] singlecycle_datapath.program_counter.value[6] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][7] singlecycle_datapath.program_counter.value[7] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][8] singlecycle_datapath.program_counter.value[8] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][9] singlecycle_datapath.program_counter.value[9] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][10] singlecycle_datapath.program_counter.value[10] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][11] singlecycle_datapath.program_counter.value[11] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][12] singlecycle_datapath.program_counter.value[12] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][13] singlecycle_datapath.program_counter.value[13] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][14] singlecycle_datapath.program_counter.value[14] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][15] singlecycle_datapath.program_counter.value[15] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][16] singlecycle_datapath.program_counter.value[16] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][17] singlecycle_datapath.program_counter.value[17] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][18] singlecycle_datapath.program_counter.value[18] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][19] singlecycle_datapath.program_counter.value[19] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][20] singlecycle_datapath.program_counter.value[20] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][21] singlecycle_datapath.program_counter.value[21] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][22] singlecycle_datapath.program_counter.value[22] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][23] singlecycle_datapath.program_counter.value[23] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][24] singlecycle_datapath.program_counter.value[24] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][25] singlecycle_datapath.program_counter.value[25] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][26] singlecycle_datapath.program_counter.value[26] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][27] singlecycle_datapath.program_counter.value[27] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][28] singlecycle_datapath.program_counter.value[28] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][29] singlecycle_datapath.program_counter.value[29] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][30] singlecycle_datapath.program_counter.value[30] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][31] singlecycle_datapath.program_counter.value[31] re clock 2
+.names bus_address[0] address[0]
+1 1
+.names bus_address[1] address[1]
+1 1
+.names bus_address[2] address[2]
+1 1
+.names bus_address[3] address[3]
+1 1
+.names bus_address[4] address[4]
+1 1
+.names bus_address[5] address[5]
+1 1
+.names bus_address[6] address[6]
+1 1
+.names bus_address[7] address[7]
+1 1
+.names bus_address[8] address[8]
+1 1
+.names bus_address[9] address[9]
+1 1
+.names bus_address[10] address[10]
+1 1
+.names bus_address[11] address[11]
+1 1
+.names bus_address[12] address[12]
+1 1
+.names bus_address[13] address[13]
+1 1
+.names bus_address[14] address[14]
+1 1
+.names bus_address[15] address[15]
+1 1
+.names bus_address[16] address[16]
+1 1
+.names bus_address[17] address[17]
+1 1
+.names bus_address[18] address[18]
+1 1
+.names bus_address[19] address[19]
+1 1
+.names bus_address[20] address[20]
+1 1
+.names bus_address[21] address[21]
+1 1
+.names bus_address[22] address[22]
+1 1
+.names bus_address[23] address[23]
+1 1
+.names bus_address[24] address[24]
+1 1
+.names bus_address[25] address[25]
+1 1
+.names bus_address[26] address[26]
+1 1
+.names bus_address[27] address[27]
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+.names bus_address[28] address[28]
+1 1
+.names bus_address[29] address[29]
+1 1
+.names bus_address[30] address[30]
+1 1
+.names bus_address[31] address[31]
+1 1
+.names $false alu_function[4]
+1 1
+.names bus_address[0] data_memory_interface.address[0]
+1 1
+.names bus_address[1] data_memory_interface.address[1]
+1 1
+.names bus_address[2] data_memory_interface.address[2]
+1 1
+.names bus_address[3] data_memory_interface.address[3]
+1 1
+.names bus_address[4] data_memory_interface.address[4]
+1 1
+.names bus_address[5] data_memory_interface.address[5]
+1 1
+.names bus_address[6] data_memory_interface.address[6]
+1 1
+.names bus_address[7] data_memory_interface.address[7]
+1 1
+.names bus_address[8] data_memory_interface.address[8]
+1 1
+.names bus_address[9] data_memory_interface.address[9]
+1 1
+.names bus_address[10] data_memory_interface.address[10]
+1 1
+.names bus_address[11] data_memory_interface.address[11]
+1 1
+.names bus_address[12] data_memory_interface.address[12]
+1 1
+.names bus_address[13] data_memory_interface.address[13]
+1 1
+.names bus_address[14] data_memory_interface.address[14]
+1 1
+.names bus_address[15] data_memory_interface.address[15]
+1 1
+.names bus_address[16] data_memory_interface.address[16]
+1 1
+.names bus_address[17] data_memory_interface.address[17]
+1 1
+.names bus_address[18] data_memory_interface.address[18]
+1 1
+.names bus_address[19] data_memory_interface.address[19]
+1 1
+.names bus_address[20] data_memory_interface.address[20]
+1 1
+.names bus_address[21] data_memory_interface.address[21]
+1 1
+.names bus_address[22] data_memory_interface.address[22]
+1 1
+.names bus_address[23] data_memory_interface.address[23]
+1 1
+.names bus_address[24] data_memory_interface.address[24]
+1 1
+.names bus_address[25] data_memory_interface.address[25]
+1 1
+.names bus_address[26] data_memory_interface.address[26]
+1 1
+.names bus_address[27] data_memory_interface.address[27]
+1 1
+.names bus_address[28] data_memory_interface.address[28]
+1 1
+.names bus_address[29] data_memory_interface.address[29]
+1 1
+.names bus_address[30] data_memory_interface.address[30]
+1 1
+.names bus_address[31] data_memory_interface.address[31]
+1 1
+.names bus_address[0] data_memory_interface.bus_address[0]
+1 1
+.names bus_address[1] data_memory_interface.bus_address[1]
+1 1
+.names bus_address[2] data_memory_interface.bus_address[2]
+1 1
+.names bus_address[3] data_memory_interface.bus_address[3]
+1 1
+.names bus_address[4] data_memory_interface.bus_address[4]
+1 1
+.names bus_address[5] data_memory_interface.bus_address[5]
+1 1
+.names bus_address[6] data_memory_interface.bus_address[6]
+1 1
+.names bus_address[7] data_memory_interface.bus_address[7]
+1 1
+.names bus_address[8] data_memory_interface.bus_address[8]
+1 1
+.names bus_address[9] data_memory_interface.bus_address[9]
+1 1
+.names bus_address[10] data_memory_interface.bus_address[10]
+1 1
+.names bus_address[11] data_memory_interface.bus_address[11]
+1 1
+.names bus_address[12] data_memory_interface.bus_address[12]
+1 1
+.names bus_address[13] data_memory_interface.bus_address[13]
+1 1
+.names bus_address[14] data_memory_interface.bus_address[14]
+1 1
+.names bus_address[15] data_memory_interface.bus_address[15]
+1 1
+.names bus_address[16] data_memory_interface.bus_address[16]
+1 1
+.names bus_address[17] data_memory_interface.bus_address[17]
+1 1
+.names bus_address[18] data_memory_interface.bus_address[18]
+1 1
+.names bus_address[19] data_memory_interface.bus_address[19]
+1 1
+.names bus_address[20] data_memory_interface.bus_address[20]
+1 1
+.names bus_address[21] data_memory_interface.bus_address[21]
+1 1
+.names bus_address[22] data_memory_interface.bus_address[22]
+1 1
+.names bus_address[23] data_memory_interface.bus_address[23]
+1 1
+.names bus_address[24] data_memory_interface.bus_address[24]
+1 1
+.names bus_address[25] data_memory_interface.bus_address[25]
+1 1
+.names bus_address[26] data_memory_interface.bus_address[26]
+1 1
+.names bus_address[27] data_memory_interface.bus_address[27]
+1 1
+.names bus_address[28] data_memory_interface.bus_address[28]
+1 1
+.names bus_address[29] data_memory_interface.bus_address[29]
+1 1
+.names bus_address[30] data_memory_interface.bus_address[30]
+1 1
+.names bus_address[31] data_memory_interface.bus_address[31]
+1 1
+.names bus_byte_enable[0] data_memory_interface.bus_byte_enable[0]
+1 1
+.names bus_byte_enable[1] data_memory_interface.bus_byte_enable[1]
+1 1
+.names bus_byte_enable[2] data_memory_interface.bus_byte_enable[2]
+1 1
+.names bus_byte_enable[3] data_memory_interface.bus_byte_enable[3]
+1 1
+.names bus_read_data[0] data_memory_interface.bus_read_data[0]
+1 1
+.names bus_read_data[1] data_memory_interface.bus_read_data[1]
+1 1
+.names bus_read_data[2] data_memory_interface.bus_read_data[2]
+1 1
+.names bus_read_data[3] data_memory_interface.bus_read_data[3]
+1 1
+.names bus_read_data[4] data_memory_interface.bus_read_data[4]
+1 1
+.names bus_read_data[5] data_memory_interface.bus_read_data[5]
+1 1
+.names bus_read_data[6] data_memory_interface.bus_read_data[6]
+1 1
+.names bus_read_data[7] data_memory_interface.bus_read_data[7]
+1 1
+.names bus_read_data[8] data_memory_interface.bus_read_data[8]
+1 1
+.names bus_read_data[9] data_memory_interface.bus_read_data[9]
+1 1
+.names bus_read_data[10] data_memory_interface.bus_read_data[10]
+1 1
+.names bus_read_data[11] data_memory_interface.bus_read_data[11]
+1 1
+.names bus_read_data[12] data_memory_interface.bus_read_data[12]
+1 1
+.names bus_read_data[13] data_memory_interface.bus_read_data[13]
+1 1
+.names bus_read_data[14] data_memory_interface.bus_read_data[14]
+1 1
+.names bus_read_data[15] data_memory_interface.bus_read_data[15]
+1 1
+.names bus_read_data[16] data_memory_interface.bus_read_data[16]
+1 1
+.names bus_read_data[17] data_memory_interface.bus_read_data[17]
+1 1
+.names bus_read_data[18] data_memory_interface.bus_read_data[18]
+1 1
+.names bus_read_data[19] data_memory_interface.bus_read_data[19]
+1 1
+.names bus_read_data[20] data_memory_interface.bus_read_data[20]
+1 1
+.names bus_read_data[21] data_memory_interface.bus_read_data[21]
+1 1
+.names bus_read_data[22] data_memory_interface.bus_read_data[22]
+1 1
+.names bus_read_data[23] data_memory_interface.bus_read_data[23]
+1 1
+.names bus_read_data[24] data_memory_interface.bus_read_data[24]
+1 1
+.names bus_read_data[25] data_memory_interface.bus_read_data[25]
+1 1
+.names bus_read_data[26] data_memory_interface.bus_read_data[26]
+1 1
+.names bus_read_data[27] data_memory_interface.bus_read_data[27]
+1 1
+.names bus_read_data[28] data_memory_interface.bus_read_data[28]
+1 1
+.names bus_read_data[29] data_memory_interface.bus_read_data[29]
+1 1
+.names bus_read_data[30] data_memory_interface.bus_read_data[30]
+1 1
+.names bus_read_data[31] data_memory_interface.bus_read_data[31]
+1 1
+.names bus_read_enable data_memory_interface.bus_read_enable
+1 1
+.names bus_write_data[0] data_memory_interface.bus_write_data[0]
+1 1
+.names bus_write_data[1] data_memory_interface.bus_write_data[1]
+1 1
+.names bus_write_data[2] data_memory_interface.bus_write_data[2]
+1 1
+.names bus_write_data[3] data_memory_interface.bus_write_data[3]
+1 1
+.names bus_write_data[4] data_memory_interface.bus_write_data[4]
+1 1
+.names bus_write_data[5] data_memory_interface.bus_write_data[5]
+1 1
+.names bus_write_data[6] data_memory_interface.bus_write_data[6]
+1 1
+.names bus_write_data[7] data_memory_interface.bus_write_data[7]
+1 1
+.names bus_write_data[8] data_memory_interface.bus_write_data[8]
+1 1
+.names bus_write_data[9] data_memory_interface.bus_write_data[9]
+1 1
+.names bus_write_data[10] data_memory_interface.bus_write_data[10]
+1 1
+.names bus_write_data[11] data_memory_interface.bus_write_data[11]
+1 1
+.names bus_write_data[12] data_memory_interface.bus_write_data[12]
+1 1
+.names bus_write_data[13] data_memory_interface.bus_write_data[13]
+1 1
+.names bus_write_data[14] data_memory_interface.bus_write_data[14]
+1 1
+.names bus_write_data[15] data_memory_interface.bus_write_data[15]
+1 1
+.names bus_write_data[16] data_memory_interface.bus_write_data[16]
+1 1
+.names bus_write_data[17] data_memory_interface.bus_write_data[17]
+1 1
+.names bus_write_data[18] data_memory_interface.bus_write_data[18]
+1 1
+.names bus_write_data[19] data_memory_interface.bus_write_data[19]
+1 1
+.names bus_write_data[20] data_memory_interface.bus_write_data[20]
+1 1
+.names bus_write_data[21] data_memory_interface.bus_write_data[21]
+1 1
+.names bus_write_data[22] data_memory_interface.bus_write_data[22]
+1 1
+.names bus_write_data[23] data_memory_interface.bus_write_data[23]
+1 1
+.names bus_write_data[24] data_memory_interface.bus_write_data[24]
+1 1
+.names bus_write_data[25] data_memory_interface.bus_write_data[25]
+1 1
+.names bus_write_data[26] data_memory_interface.bus_write_data[26]
+1 1
+.names bus_write_data[27] data_memory_interface.bus_write_data[27]
+1 1
+.names bus_write_data[28] data_memory_interface.bus_write_data[28]
+1 1
+.names bus_write_data[29] data_memory_interface.bus_write_data[29]
+1 1
+.names bus_write_data[30] data_memory_interface.bus_write_data[30]
+1 1
+.names bus_write_data[31] data_memory_interface.bus_write_data[31]
+1 1
+.names bus_write_enable data_memory_interface.bus_write_enable
+1 1
+.names clock data_memory_interface.clock
+1 1
+.names inst[12] data_memory_interface.data_format[0]
+1 1
+.names inst[13] data_memory_interface.data_format[1]
+1 1
+.names inst[14] data_memory_interface.data_format[2]
+1 1
+.names bus_read_enable data_memory_interface.read_enable
+1 1
+.names rs2_data[0] data_memory_interface.write_data[0]
+1 1
+.names rs2_data[1] data_memory_interface.write_data[1]
+1 1
+.names rs2_data[2] data_memory_interface.write_data[2]
+1 1
+.names rs2_data[3] data_memory_interface.write_data[3]
+1 1
+.names rs2_data[4] data_memory_interface.write_data[4]
+1 1
+.names rs2_data[5] data_memory_interface.write_data[5]
+1 1
+.names rs2_data[6] data_memory_interface.write_data[6]
+1 1
+.names rs2_data[7] data_memory_interface.write_data[7]
+1 1
+.names rs2_data[8] data_memory_interface.write_data[8]
+1 1
+.names rs2_data[9] data_memory_interface.write_data[9]
+1 1
+.names rs2_data[10] data_memory_interface.write_data[10]
+1 1
+.names rs2_data[11] data_memory_interface.write_data[11]
+1 1
+.names rs2_data[12] data_memory_interface.write_data[12]
+1 1
+.names rs2_data[13] data_memory_interface.write_data[13]
+1 1
+.names rs2_data[14] data_memory_interface.write_data[14]
+1 1
+.names rs2_data[15] data_memory_interface.write_data[15]
+1 1
+.names rs2_data[16] data_memory_interface.write_data[16]
+1 1
+.names rs2_data[17] data_memory_interface.write_data[17]
+1 1
+.names rs2_data[18] data_memory_interface.write_data[18]
+1 1
+.names rs2_data[19] data_memory_interface.write_data[19]
+1 1
+.names rs2_data[20] data_memory_interface.write_data[20]
+1 1
+.names rs2_data[21] data_memory_interface.write_data[21]
+1 1
+.names rs2_data[22] data_memory_interface.write_data[22]
+1 1
+.names rs2_data[23] data_memory_interface.write_data[23]
+1 1
+.names rs2_data[24] data_memory_interface.write_data[24]
+1 1
+.names rs2_data[25] data_memory_interface.write_data[25]
+1 1
+.names rs2_data[26] data_memory_interface.write_data[26]
+1 1
+.names rs2_data[27] data_memory_interface.write_data[27]
+1 1
+.names rs2_data[28] data_memory_interface.write_data[28]
+1 1
+.names rs2_data[29] data_memory_interface.write_data[29]
+1 1
+.names rs2_data[30] data_memory_interface.write_data[30]
+1 1
+.names rs2_data[31] data_memory_interface.write_data[31]
+1 1
+.names bus_write_enable data_memory_interface.write_enable
+1 1
+.names inst[12] inst_funct3[0]
+1 1
+.names inst[13] inst_funct3[1]
+1 1
+.names inst[14] inst_funct3[2]
+1 1
+.names inst[25] inst_funct7[0]
+1 1
+.names inst[26] inst_funct7[1]
+1 1
+.names inst[27] inst_funct7[2]
+1 1
+.names inst[28] inst_funct7[3]
+1 1
+.names inst[29] inst_funct7[4]
+1 1
+.names inst[30] inst_funct7[5]
+1 1
+.names inst[31] inst_funct7[6]
+1 1
+.names inst[0] inst_opcode[0]
+1 1
+.names inst[1] inst_opcode[1]
+1 1
+.names inst[2] inst_opcode[2]
+1 1
+.names inst[3] inst_opcode[3]
+1 1
+.names inst[4] inst_opcode[4]
+1 1
+.names inst[5] inst_opcode[5]
+1 1
+.names inst[6] inst_opcode[6]
+1 1
+.names singlecycle_datapath.program_counter.value[0] pc[0]
+1 1
+.names singlecycle_datapath.program_counter.value[1] pc[1]
+1 1
+.names singlecycle_datapath.program_counter.value[2] pc[2]
+1 1
+.names singlecycle_datapath.program_counter.value[3] pc[3]
+1 1
+.names singlecycle_datapath.program_counter.value[4] pc[4]
+1 1
+.names singlecycle_datapath.program_counter.value[5] pc[5]
+1 1
+.names singlecycle_datapath.program_counter.value[6] pc[6]
+1 1
+.names singlecycle_datapath.program_counter.value[7] pc[7]
+1 1
+.names singlecycle_datapath.program_counter.value[8] pc[8]
+1 1
+.names singlecycle_datapath.program_counter.value[9] pc[9]
+1 1
+.names singlecycle_datapath.program_counter.value[10] pc[10]
+1 1
+.names singlecycle_datapath.program_counter.value[11] pc[11]
+1 1
+.names singlecycle_datapath.program_counter.value[12] pc[12]
+1 1
+.names singlecycle_datapath.program_counter.value[13] pc[13]
+1 1
+.names singlecycle_datapath.program_counter.value[14] pc[14]
+1 1
+.names singlecycle_datapath.program_counter.value[15] pc[15]
+1 1
+.names singlecycle_datapath.program_counter.value[16] pc[16]
+1 1
+.names singlecycle_datapath.program_counter.value[17] pc[17]
+1 1
+.names singlecycle_datapath.program_counter.value[18] pc[18]
+1 1
+.names singlecycle_datapath.program_counter.value[19] pc[19]
+1 1
+.names singlecycle_datapath.program_counter.value[20] pc[20]
+1 1
+.names singlecycle_datapath.program_counter.value[21] pc[21]
+1 1
+.names singlecycle_datapath.program_counter.value[22] pc[22]
+1 1
+.names singlecycle_datapath.program_counter.value[23] pc[23]
+1 1
+.names singlecycle_datapath.program_counter.value[24] pc[24]
+1 1
+.names singlecycle_datapath.program_counter.value[25] pc[25]
+1 1
+.names singlecycle_datapath.program_counter.value[26] pc[26]
+1 1
+.names singlecycle_datapath.program_counter.value[27] pc[27]
+1 1
+.names singlecycle_datapath.program_counter.value[28] pc[28]
+1 1
+.names singlecycle_datapath.program_counter.value[29] pc[29]
+1 1
+.names singlecycle_datapath.program_counter.value[30] pc[30]
+1 1
+.names singlecycle_datapath.program_counter.value[31] pc[31]
+1 1
+.names $true pc_write_enable
+1 1
+.names inst[7] rd_address[0]
+1 1
+.names $false rd_address[1]
+1 1
+.names $false rd_address[2]
+1 1
+.names $false rd_address[3]
+1 1
+.names $false rd_address[4]
+1 1
+.names bus_read_enable read_enable
+1 1
+.names inst[15] rs1_address[0]
+1 1
+.names $false rs1_address[1]
+1 1
+.names $false rs1_address[2]
+1 1
+.names $false rs1_address[3]
+1 1
+.names $false rs1_address[4]
+1 1
+.names inst[20] rs2_address[0]
+1 1
+.names $false rs2_address[1]
+1 1
+.names $false rs2_address[2]
+1 1
+.names $false rs2_address[3]
+1 1
+.names $false rs2_address[4]
+1 1
+.names alu_function[0] singlecycle_ctlpath.alu_control.alu_function[0]
+1 1
+.names alu_function[1] singlecycle_ctlpath.alu_control.alu_function[1]
+1 1
+.names alu_function[2] singlecycle_ctlpath.alu_control.alu_function[2]
+1 1
+.names alu_function[3] singlecycle_ctlpath.alu_control.alu_function[3]
+1 1
+.names $false singlecycle_ctlpath.alu_control.alu_function[4]
+1 1
+.names singlecycle_ctlpath.alu_control.branch_funct[2] singlecycle_ctlpath.alu_control.branch_funct[1]
+1 1
+.names inst[12] singlecycle_ctlpath.alu_control.inst_funct3[0]
+1 1
+.names inst[13] singlecycle_ctlpath.alu_control.inst_funct3[1]
+1 1
+.names inst[14] singlecycle_ctlpath.alu_control.inst_funct3[2]
+1 1
+.names inst[25] singlecycle_ctlpath.alu_control.inst_funct7[0]
+1 1
+.names inst[26] singlecycle_ctlpath.alu_control.inst_funct7[1]
+1 1
+.names inst[27] singlecycle_ctlpath.alu_control.inst_funct7[2]
+1 1
+.names inst[28] singlecycle_ctlpath.alu_control.inst_funct7[3]
+1 1
+.names inst[29] singlecycle_ctlpath.alu_control.inst_funct7[4]
+1 1
+.names inst[30] singlecycle_ctlpath.alu_control.inst_funct7[5]
+1 1
+.names inst[31] singlecycle_ctlpath.alu_control.inst_funct7[6]
+1 1
+.names $false singlecycle_ctlpath.alu_control.op_funct[4]
+1 1
+.names $false singlecycle_ctlpath.alu_control.op_imm_funct[4]
+1 1
+.names alu_function[0] singlecycle_ctlpath.alu_function[0]
+1 1
+.names alu_function[1] singlecycle_ctlpath.alu_function[1]
+1 1
+.names alu_function[2] singlecycle_ctlpath.alu_function[2]
+1 1
+.names alu_function[3] singlecycle_ctlpath.alu_function[3]
+1 1
+.names $false singlecycle_ctlpath.alu_function[4]
+1 1
+.names inst[12] singlecycle_ctlpath.control_transfer.inst_funct3[0]
+1 1
+.names inst[13] singlecycle_ctlpath.control_transfer.inst_funct3[1]
+1 1
+.names inst[14] singlecycle_ctlpath.control_transfer.inst_funct3[2]
+1 1
+.names bus_read_enable singlecycle_ctlpath.data_mem_read_enable
+1 1
+.names bus_write_enable singlecycle_ctlpath.data_mem_write_enable
+1 1
+.names inst[12] singlecycle_ctlpath.inst_funct3[0]
+1 1
+.names inst[13] singlecycle_ctlpath.inst_funct3[1]
+1 1
+.names inst[14] singlecycle_ctlpath.inst_funct3[2]
+1 1
+.names inst[25] singlecycle_ctlpath.inst_funct7[0]
+1 1
+.names inst[26] singlecycle_ctlpath.inst_funct7[1]
+1 1
+.names inst[27] singlecycle_ctlpath.inst_funct7[2]
+1 1
+.names inst[28] singlecycle_ctlpath.inst_funct7[3]
+1 1
+.names inst[29] singlecycle_ctlpath.inst_funct7[4]
+1 1
+.names inst[30] singlecycle_ctlpath.inst_funct7[5]
+1 1
+.names inst[31] singlecycle_ctlpath.inst_funct7[6]
+1 1
+.names inst[0] singlecycle_ctlpath.inst_opcode[0]
+1 1
+.names inst[1] singlecycle_ctlpath.inst_opcode[1]
+1 1
+.names inst[2] singlecycle_ctlpath.inst_opcode[2]
+1 1
+.names inst[3] singlecycle_ctlpath.inst_opcode[3]
+1 1
+.names inst[4] singlecycle_ctlpath.inst_opcode[4]
+1 1
+.names inst[5] singlecycle_ctlpath.inst_opcode[5]
+1 1
+.names inst[6] singlecycle_ctlpath.inst_opcode[6]
+1 1
+.names $true singlecycle_ctlpath.pc_write_enable
+1 1
+.names $false singlecycle_ctlpath.reg_writeback_select[2]
+1 1
+.names regfile_write_enable singlecycle_ctlpath.regfile_write_enable
+1 1
+.names bus_read_enable singlecycle_ctlpath.singlecycle_control.data_mem_read_enable
+1 1
+.names bus_write_enable singlecycle_ctlpath.singlecycle_control.data_mem_write_enable
+1 1
+.names inst[0] singlecycle_ctlpath.singlecycle_control.inst_opcode[0]
+1 1
+.names inst[1] singlecycle_ctlpath.singlecycle_control.inst_opcode[1]
+1 1
+.names inst[2] singlecycle_ctlpath.singlecycle_control.inst_opcode[2]
+1 1
+.names inst[3] singlecycle_ctlpath.singlecycle_control.inst_opcode[3]
+1 1
+.names inst[4] singlecycle_ctlpath.singlecycle_control.inst_opcode[4]
+1 1
+.names inst[5] singlecycle_ctlpath.singlecycle_control.inst_opcode[5]
+1 1
+.names inst[6] singlecycle_ctlpath.singlecycle_control.inst_opcode[6]
+1 1
+.names $true singlecycle_ctlpath.singlecycle_control.pc_write_enable
+1 1
+.names $false singlecycle_ctlpath.singlecycle_control.reg_writeback_select[2]
+1 1
+.names regfile_write_enable singlecycle_ctlpath.singlecycle_control.regfile_write_enable
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[0]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[1]
+1 1
+.names $true singlecycle_datapath.adder_pc_plus_4.operand_a[2]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[3]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[4]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[5]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[6]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[7]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[8]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[9]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[10]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[11]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[12]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[13]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[14]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[15]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[16]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[17]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[18]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[19]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[20]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[21]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[22]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[23]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[24]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[25]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[26]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[27]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[28]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[29]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[30]
+1 1
+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[31]
+1 1
+.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.adder_pc_plus_4.operand_b[0]
+1 1
+.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.adder_pc_plus_4.operand_b[1]
+1 1
+.names singlecycle_datapath.program_counter.value[2] singlecycle_datapath.adder_pc_plus_4.operand_b[2]
+1 1
+.names singlecycle_datapath.program_counter.value[3] singlecycle_datapath.adder_pc_plus_4.operand_b[3]
+1 1
+.names singlecycle_datapath.program_counter.value[4] singlecycle_datapath.adder_pc_plus_4.operand_b[4]
+1 1
+.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.adder_pc_plus_4.operand_b[5]
+1 1
+.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.adder_pc_plus_4.operand_b[6]
+1 1
+.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.adder_pc_plus_4.operand_b[7]
+1 1
+.names singlecycle_datapath.program_counter.value[8] singlecycle_datapath.adder_pc_plus_4.operand_b[8]
+1 1
+.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.adder_pc_plus_4.operand_b[9]
+1 1
+.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.adder_pc_plus_4.operand_b[10]
+1 1
+.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.adder_pc_plus_4.operand_b[11]
+1 1
+.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.adder_pc_plus_4.operand_b[12]
+1 1
+.names singlecycle_datapath.program_counter.value[13] singlecycle_datapath.adder_pc_plus_4.operand_b[13]
+1 1
+.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.adder_pc_plus_4.operand_b[14]
+1 1
+.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.adder_pc_plus_4.operand_b[15]
+1 1
+.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.adder_pc_plus_4.operand_b[16]
+1 1
+.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.adder_pc_plus_4.operand_b[17]
+1 1
+.names singlecycle_datapath.program_counter.value[18] singlecycle_datapath.adder_pc_plus_4.operand_b[18]
+1 1
+.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.adder_pc_plus_4.operand_b[19]
+1 1
+.names singlecycle_datapath.program_counter.value[20] singlecycle_datapath.adder_pc_plus_4.operand_b[20]
+1 1
+.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.adder_pc_plus_4.operand_b[21]
+1 1
+.names singlecycle_datapath.program_counter.value[22] singlecycle_datapath.adder_pc_plus_4.operand_b[22]
+1 1
+.names singlecycle_datapath.program_counter.value[23] singlecycle_datapath.adder_pc_plus_4.operand_b[23]
+1 1
+.names singlecycle_datapath.program_counter.value[24] singlecycle_datapath.adder_pc_plus_4.operand_b[24]
+1 1
+.names singlecycle_datapath.program_counter.value[25] singlecycle_datapath.adder_pc_plus_4.operand_b[25]
+1 1
+.names singlecycle_datapath.program_counter.value[26] singlecycle_datapath.adder_pc_plus_4.operand_b[26]
+1 1
+.names singlecycle_datapath.program_counter.value[27] singlecycle_datapath.adder_pc_plus_4.operand_b[27]
+1 1
+.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.adder_pc_plus_4.operand_b[28]
+1 1
+.names singlecycle_datapath.program_counter.value[29] singlecycle_datapath.adder_pc_plus_4.operand_b[29]
+1 1
+.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.adder_pc_plus_4.operand_b[30]
+1 1
+.names singlecycle_datapath.program_counter.value[31] singlecycle_datapath.adder_pc_plus_4.operand_b[31]
+1 1
+.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.adder_pc_plus_4.result[0]
+1 1
+.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.adder_pc_plus_4.result[1]
+1 1
+.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.adder_pc_plus_immediate.operand_a[0]
+1 1
+.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.adder_pc_plus_immediate.operand_a[1]
+1 1
+.names singlecycle_datapath.program_counter.value[2] singlecycle_datapath.adder_pc_plus_immediate.operand_a[2]
+1 1
+.names singlecycle_datapath.program_counter.value[3] singlecycle_datapath.adder_pc_plus_immediate.operand_a[3]
+1 1
+.names singlecycle_datapath.program_counter.value[4] singlecycle_datapath.adder_pc_plus_immediate.operand_a[4]
+1 1
+.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.adder_pc_plus_immediate.operand_a[5]
+1 1
+.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.adder_pc_plus_immediate.operand_a[6]
+1 1
+.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.adder_pc_plus_immediate.operand_a[7]
+1 1
+.names singlecycle_datapath.program_counter.value[8] singlecycle_datapath.adder_pc_plus_immediate.operand_a[8]
+1 1
+.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.adder_pc_plus_immediate.operand_a[9]
+1 1
+.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.adder_pc_plus_immediate.operand_a[10]
+1 1
+.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.adder_pc_plus_immediate.operand_a[11]
+1 1
+.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.adder_pc_plus_immediate.operand_a[12]
+1 1
+.names singlecycle_datapath.program_counter.value[13] singlecycle_datapath.adder_pc_plus_immediate.operand_a[13]
+1 1
+.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.adder_pc_plus_immediate.operand_a[14]
+1 1
+.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.adder_pc_plus_immediate.operand_a[15]
+1 1
+.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.adder_pc_plus_immediate.operand_a[16]
+1 1
+.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.adder_pc_plus_immediate.operand_a[17]
+1 1
+.names singlecycle_datapath.program_counter.value[18] singlecycle_datapath.adder_pc_plus_immediate.operand_a[18]
+1 1
+.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.adder_pc_plus_immediate.operand_a[19]
+1 1
+.names singlecycle_datapath.program_counter.value[20] singlecycle_datapath.adder_pc_plus_immediate.operand_a[20]
+1 1
+.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.adder_pc_plus_immediate.operand_a[21]
+1 1
+.names singlecycle_datapath.program_counter.value[22] singlecycle_datapath.adder_pc_plus_immediate.operand_a[22]
+1 1
+.names singlecycle_datapath.program_counter.value[23] singlecycle_datapath.adder_pc_plus_immediate.operand_a[23]
+1 1
+.names singlecycle_datapath.program_counter.value[24] singlecycle_datapath.adder_pc_plus_immediate.operand_a[24]
+1 1
+.names singlecycle_datapath.program_counter.value[25] singlecycle_datapath.adder_pc_plus_immediate.operand_a[25]
+1 1
+.names singlecycle_datapath.program_counter.value[26] singlecycle_datapath.adder_pc_plus_immediate.operand_a[26]
+1 1
+.names singlecycle_datapath.program_counter.value[27] singlecycle_datapath.adder_pc_plus_immediate.operand_a[27]
+1 1
+.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.adder_pc_plus_immediate.operand_a[28]
+1 1
+.names singlecycle_datapath.program_counter.value[29] singlecycle_datapath.adder_pc_plus_immediate.operand_a[29]
+1 1
+.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.adder_pc_plus_immediate.operand_a[30]
+1 1
+.names singlecycle_datapath.program_counter.value[31] singlecycle_datapath.adder_pc_plus_immediate.operand_a[31]
+1 1
+.names alu_function[0] singlecycle_datapath.alu.alu_function[0]
+1 1
+.names alu_function[1] singlecycle_datapath.alu.alu_function[1]
+1 1
+.names alu_function[2] singlecycle_datapath.alu.alu_function[2]
+1 1
+.names alu_function[3] singlecycle_datapath.alu.alu_function[3]
+1 1
+.names $false singlecycle_datapath.alu.alu_function[4]
+1 1
+.names bus_address[0] singlecycle_datapath.alu.result[0]
+1 1
+.names bus_address[1] singlecycle_datapath.alu.result[1]
+1 1
+.names bus_address[2] singlecycle_datapath.alu.result[2]
+1 1
+.names bus_address[3] singlecycle_datapath.alu.result[3]
+1 1
+.names bus_address[4] singlecycle_datapath.alu.result[4]
+1 1
+.names bus_address[5] singlecycle_datapath.alu.result[5]
+1 1
+.names bus_address[6] singlecycle_datapath.alu.result[6]
+1 1
+.names bus_address[7] singlecycle_datapath.alu.result[7]
+1 1
+.names bus_address[8] singlecycle_datapath.alu.result[8]
+1 1
+.names bus_address[9] singlecycle_datapath.alu.result[9]
+1 1
+.names bus_address[10] singlecycle_datapath.alu.result[10]
+1 1
+.names bus_address[11] singlecycle_datapath.alu.result[11]
+1 1
+.names bus_address[12] singlecycle_datapath.alu.result[12]
+1 1
+.names bus_address[13] singlecycle_datapath.alu.result[13]
+1 1
+.names bus_address[14] singlecycle_datapath.alu.result[14]
+1 1
+.names bus_address[15] singlecycle_datapath.alu.result[15]
+1 1
+.names bus_address[16] singlecycle_datapath.alu.result[16]
+1 1
+.names bus_address[17] singlecycle_datapath.alu.result[17]
+1 1
+.names bus_address[18] singlecycle_datapath.alu.result[18]
+1 1
+.names bus_address[19] singlecycle_datapath.alu.result[19]
+1 1
+.names bus_address[20] singlecycle_datapath.alu.result[20]
+1 1
+.names bus_address[21] singlecycle_datapath.alu.result[21]
+1 1
+.names bus_address[22] singlecycle_datapath.alu.result[22]
+1 1
+.names bus_address[23] singlecycle_datapath.alu.result[23]
+1 1
+.names bus_address[24] singlecycle_datapath.alu.result[24]
+1 1
+.names bus_address[25] singlecycle_datapath.alu.result[25]
+1 1
+.names bus_address[26] singlecycle_datapath.alu.result[26]
+1 1
+.names bus_address[27] singlecycle_datapath.alu.result[27]
+1 1
+.names bus_address[28] singlecycle_datapath.alu.result[28]
+1 1
+.names bus_address[29] singlecycle_datapath.alu.result[29]
+1 1
+.names bus_address[30] singlecycle_datapath.alu.result[30]
+1 1
+.names bus_address[31] singlecycle_datapath.alu.result[31]
+1 1
+.names alu_function[0] singlecycle_datapath.alu_function[0]
+1 1
+.names alu_function[1] singlecycle_datapath.alu_function[1]
+1 1
+.names alu_function[2] singlecycle_datapath.alu_function[2]
+1 1
+.names alu_function[3] singlecycle_datapath.alu_function[3]
+1 1
+.names $false singlecycle_datapath.alu_function[4]
+1 1
+.names bus_address[0] singlecycle_datapath.alu_result[0]
+1 1
+.names bus_address[1] singlecycle_datapath.alu_result[1]
+1 1
+.names bus_address[2] singlecycle_datapath.alu_result[2]
+1 1
+.names bus_address[3] singlecycle_datapath.alu_result[3]
+1 1
+.names bus_address[4] singlecycle_datapath.alu_result[4]
+1 1
+.names bus_address[5] singlecycle_datapath.alu_result[5]
+1 1
+.names bus_address[6] singlecycle_datapath.alu_result[6]
+1 1
+.names bus_address[7] singlecycle_datapath.alu_result[7]
+1 1
+.names bus_address[8] singlecycle_datapath.alu_result[8]
+1 1
+.names bus_address[9] singlecycle_datapath.alu_result[9]
+1 1
+.names bus_address[10] singlecycle_datapath.alu_result[10]
+1 1
+.names bus_address[11] singlecycle_datapath.alu_result[11]
+1 1
+.names bus_address[12] singlecycle_datapath.alu_result[12]
+1 1
+.names bus_address[13] singlecycle_datapath.alu_result[13]
+1 1
+.names bus_address[14] singlecycle_datapath.alu_result[14]
+1 1
+.names bus_address[15] singlecycle_datapath.alu_result[15]
+1 1
+.names bus_address[16] singlecycle_datapath.alu_result[16]
+1 1
+.names bus_address[17] singlecycle_datapath.alu_result[17]
+1 1
+.names bus_address[18] singlecycle_datapath.alu_result[18]
+1 1
+.names bus_address[19] singlecycle_datapath.alu_result[19]
+1 1
+.names bus_address[20] singlecycle_datapath.alu_result[20]
+1 1
+.names bus_address[21] singlecycle_datapath.alu_result[21]
+1 1
+.names bus_address[22] singlecycle_datapath.alu_result[22]
+1 1
+.names bus_address[23] singlecycle_datapath.alu_result[23]
+1 1
+.names bus_address[24] singlecycle_datapath.alu_result[24]
+1 1
+.names bus_address[25] singlecycle_datapath.alu_result[25]
+1 1
+.names bus_address[26] singlecycle_datapath.alu_result[26]
+1 1
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+.names bus_address[12] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][12]
+1 1
+.names bus_address[13] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][13]
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+.names bus_address[14] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][14]
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+.names bus_address[15] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][15]
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+.names bus_address[16] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][16]
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+.names bus_address[17] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][17]
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+.names bus_address[18] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][18]
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+.names bus_address[19] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][19]
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+.names bus_address[20] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][20]
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+.names bus_address[21] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][21]
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+.names bus_address[22] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][22]
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+.names bus_address[23] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][23]
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+.names bus_address[24] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][24]
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+.names bus_address[25] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][25]
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+.names bus_address[26] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][26]
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+.names bus_address[27] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][27]
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+.names bus_address[28] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][28]
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+.names bus_address[29] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][29]
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+.names bus_address[30] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][30]
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+.names bus_address[31] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][31]
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+.names rs1_data[18] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][18]
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+.names rs1_data[19] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][19]
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+.names rs1_data[20] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][20]
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+.names rs1_data[21] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][21]
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+.names rs1_data[23] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][23]
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+.names rs1_data[25] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][25]
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+.names rs1_data[26] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][26]
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+.names rs1_data[30] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][30]
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+.names rs1_data[31] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][31]
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+.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][0]
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+.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][1]
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+.names singlecycle_datapath.program_counter.value[2] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][2]
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+.names singlecycle_datapath.program_counter.value[4] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][4]
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+.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][5]
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+.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][6]
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+.names rd_data[31] singlecycle_datapath.rd_data[31]
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+.names $false singlecycle_datapath.reg_writeback_select[2]
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+.names reset singlecycle_datapath.reset
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+.names inst[15] singlecycle_datapath.rs1_address[0]
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+.names $false singlecycle_datapath.rs1_address[1]
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+.names $false singlecycle_datapath.rs1_address[2]
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+.names $false singlecycle_datapath.rs1_address[3]
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+.names rs1_data[31] singlecycle_datapath.rs1_data[31]
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+.names inst[20] singlecycle_datapath.rs2_address[0]
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+.names $false singlecycle_datapath.rs2_address[1]
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+.names $false singlecycle_datapath.rs2_address[2]
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+.names $false singlecycle_datapath.rs2_address[3]
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+.names $false singlecycle_datapath.rs2_address[4]
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+.names rs2_data[12] singlecycle_datapath.rs2_data[12]
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+.names rs2_data[13] singlecycle_datapath.rs2_data[13]
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+.names rs2_data[25] singlecycle_datapath.rs2_data[25]
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+.names rs2_data[30] singlecycle_datapath.rs2_data[30]
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+.names rs2_data[31] singlecycle_datapath.rs2_data[31]
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+.names rs2_data[1] write_data[1]
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+.names rs2_data[12] write_data[12]
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+.names rs2_data[14] write_data[14]
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+.names rs2_data[15] write_data[15]
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+.names rs2_data[16] write_data[16]
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+.names rs2_data[17] write_data[17]
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+.names rs2_data[18] write_data[18]
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+.names rs2_data[19] write_data[19]
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+.names rs2_data[20] write_data[20]
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+.names rs2_data[21] write_data[21]
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+.names rs2_data[23] write_data[23]
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+.names rs2_data[24] write_data[24]
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+.names rs2_data[25] write_data[25]
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+.names rs2_data[27] write_data[27]
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+.names rs2_data[29] write_data[29]
+1 1
+.names rs2_data[30] write_data[30]
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+.names rs2_data[31] write_data[31]
+1 1
+.names bus_write_enable write_enable
+1 1
+.end
diff --git a/openfpga/test_script/riscv_core.openfpga b/openfpga/test_script/riscv_core.openfpga
new file mode 100644
index 000000000..d2614df44
--- /dev/null
+++ b/openfpga/test_script/riscv_core.openfpga
@@ -0,0 +1,2 @@
+# Run VPR for the RISC-V core
+vpr ./test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ./test_blif/riscv_core_lut6.blif