[test] updating test case
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@ -22,7 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
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openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
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openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
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[ARCHITECTURES]
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_40nm.xml
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
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[BENCHMARKS]
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v
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