[test] deploy new tests
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tangxifan
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05a49278ed
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<fabric_key>
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<module name="fpga_top">
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<region id="0">
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<key id="0" name="sb_2__2_" value="0" alias="sb_2__2_"/>
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<key id="1" name="grid_clb" value="3" alias="grid_clb_2__2_"/>
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<key id="2" name="sb_0__1_" value="0" alias="sb_0__1_"/>
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<key id="3" name="cby_0__1_" value="0" alias="cby_0__1_"/>
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<key id="4" name="grid_clb" value="2" alias="grid_clb_2__1_"/>
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<key id="5" name="grid_io_left" value="0" alias="grid_io_left_0__1_"/>
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<key id="6" name="sb_1__0_" value="0" alias="sb_1__0_"/>
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<key id="7" name="sb_1__1_" value="0" alias="sb_1__1_"/>
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<key id="8" name="cbx_1__1_" value="1" alias="cbx_2__1_"/>
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<key id="9" name="cby_1__1_" value="1" alias="cby_1__2_"/>
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<key id="10" name="grid_io_right" value="0" alias="grid_io_right_3__2_"/>
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<key id="11" name="cbx_1__0_" value="1" alias="cbx_2__0_"/>
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<key id="12" name="cby_1__1_" value="0" alias="cby_1__1_"/>
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<key id="13" name="grid_io_right" value="1" alias="grid_io_right_3__1_"/>
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<key id="14" name="grid_io_bottom" value="1" alias="grid_io_bottom_1__0_"/>
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<key id="15" name="cby_2__1_" value="0" alias="cby_2__1_"/>
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<key id="16" name="sb_2__1_" value="0" alias="sb_2__1_"/>
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<key id="17" name="cbx_1__0_" value="0" alias="cbx_1__0_"/>
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<key id="18" name="grid_clb" value="1" alias="grid_clb_1__2_"/>
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<key id="19" name="cbx_1__2_" value="0" alias="cbx_1__2_"/>
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<key id="20" name="cbx_1__2_" value="1" alias="cbx_2__2_"/>
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<key id="21" name="sb_2__0_" value="0" alias="sb_2__0_"/>
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<key id="22" name="sb_1__2_" value="0" alias="sb_1__2_"/>
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<key id="23" name="cby_0__1_" value="1" alias="cby_0__2_"/>
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<key id="24" name="sb_0__0_" value="0" alias="sb_0__0_"/>
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<key id="25" name="grid_clb" value="0" alias="grid_clb_1__1_"/>
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<key id="26" name="cby_2__1_" value="1" alias="cby_2__2_"/>
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<key id="27" name="grid_io_top" value="1" alias="grid_io_top_2__3_"/>
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<key id="28" name="sb_0__2_" value="0" alias="sb_0__2_"/>
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<key id="29" name="grid_io_bottom" value="0" alias="grid_io_bottom_2__0_"/>
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<key id="30" name="cbx_1__1_" value="0" alias="cbx_1__1_"/>
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<key id="31" name="grid_io_top" value="0" alias="grid_io_top_1__3_"/>
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<key id="32" name="grid_io_left" value="1" alias="grid_io_left_0__2_"/>
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</region>
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</module>
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<module name="logical_tile_clb_mode_clb_">
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<key id="0" name="logical_tile_clb_mode_default__fle" value="1" alias="logical_tile_clb_mode_default__fle_1"/>
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<key id="1" name="logical_tile_clb_mode_default__fle" value="0" alias="logical_tile_clb_mode_default__fle_0"/>
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<key id="2" name="logical_tile_clb_mode_default__fle" value="3" alias="logical_tile_clb_mode_default__fle_3"/>
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<key id="3" name="mux_tree_size14_mem" value="0" alias="mem_fle_0_in_0"/>
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<key id="4" name="logical_tile_clb_mode_default__fle" value="2" alias="logical_tile_clb_mode_default__fle_2"/>
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<key id="5" name="mux_tree_size14_mem" value="1" alias="mem_fle_0_in_1"/>
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<key id="6" name="mux_tree_size14_mem" value="2" alias="mem_fle_0_in_2"/>
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<key id="7" name="mux_tree_size14_mem" value="3" alias="mem_fle_0_in_3"/>
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<key id="8" name="mux_tree_size14_mem" value="4" alias="mem_fle_1_in_0"/>
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<key id="9" name="mux_tree_size14_mem" value="5" alias="mem_fle_1_in_1"/>
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<key id="10" name="mux_tree_size14_mem" value="6" alias="mem_fle_1_in_2"/>
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<key id="11" name="mux_tree_size14_mem" value="7" alias="mem_fle_1_in_3"/>
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<key id="12" name="mux_tree_size14_mem" value="8" alias="mem_fle_2_in_0"/>
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<key id="13" name="mux_tree_size14_mem" value="9" alias="mem_fle_2_in_1"/>
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<key id="14" name="mux_tree_size14_mem" value="10" alias="mem_fle_2_in_2"/>
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<key id="15" name="mux_tree_size14_mem" value="11" alias="mem_fle_2_in_3"/>
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<key id="16" name="mux_tree_size14_mem" value="12" alias="mem_fle_3_in_0"/>
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<key id="17" name="mux_tree_size14_mem" value="13" alias="mem_fle_3_in_1"/>
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<key id="18" name="mux_tree_size14_mem" value="14" alias="mem_fle_3_in_2"/>
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<key id="19" name="mux_tree_size14_mem" value="15" alias="mem_fle_3_in_3"/>
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</module>
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</fabric_key>
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@ -116,6 +116,7 @@ run-task basic_tests/fabric_key/generate_random_key $@
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run-task basic_tests/fabric_key/generate_random_key_ql_memory_bank $@
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run-task basic_tests/fabric_key/load_external_key $@
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run-task basic_tests/fabric_key/load_external_key_cc_fpga $@
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run-task basic_tests/fabric_key/load_external_subkey_cc_fpga $@
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run-task basic_tests/fabric_key/load_external_key_multi_region_cc_fpga $@
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run-task basic_tests/fabric_key/load_external_key_qlbank_fpga $@
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run-task basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga $@
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@ -0,0 +1,39 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=vpr_blif
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_sample_subkey.xml
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openfpga_vpr_device_layout=2x2
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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[SYNTHESIS_PARAM]
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bench0_top = and2
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bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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bench0_chan_width = 300
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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#vpr_fpga_verilog_formal_verification_top_netlist=
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