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[core] code format

This commit is contained in:
tangxifan 2024-05-18 12:33:19 -07:00
parent 3b93bea3d1
commit 926b9e9739
3 changed files with 18 additions and 12 deletions
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3
libs/libarchopenfpga/src/arch_direct.h
View File

@ -21,7 +21,8 @@ enum class e_direct_type {
INTER_ROW,
NUM_DIRECT_TYPES
};
constexpr std::array<const char*, (size_t)e_direct_type::NUM_DIRECT_TYPES> DIRECT_TYPE_STRING = {
constexpr std::array<const char*, (size_t)e_direct_type::NUM_DIRECT_TYPES>
DIRECT_TYPE_STRING = {
{"inner_column_or_row", "part_of_cb", "inter_column", "inter_row"}};
enum e_direct_direction { POSITIVE_DIR, NEGATIVE_DIR, NUM_DIRECT_DIRECTIONS };

12
libs/libarchopenfpga/src/read_xml_routing_circuit.cpp
View File

@ -279,21 +279,23 @@ ArchDirect read_xml_direct_circuit(pugi::xml_node& Node,
/* Add more information*/
std::string direct_type_name =
get_attribute(xml_direct, "type", loc_data, pugiutil::ReqOpt::OPTIONAL)
.as_string(DIRECT_TYPE_STRING[size_t(e_direct_type::INNER_COLUMN_OR_ROW)]);
.as_string(
DIRECT_TYPE_STRING[size_t(e_direct_type::INNER_COLUMN_OR_ROW)]);
e_direct_type direct_type = string_to_direct_type(direct_type_name);
if (e_direct_type::NUM_DIRECT_TYPES == direct_type) {
archfpga_throw(
loc_data.filename_c_str(), loc_data.line(xml_direct),
"Direct type '%s' is not support! Acceptable values are [inner_column_or_row|part_of_cb|column|row]\n",
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_direct),
"Direct type '%s' is not support! Acceptable values are "
"[inner_column_or_row|part_of_cb|column|row]\n",
direct_type_name.c_str());
}
arch_direct.set_type(direct, direct_type);
/* The following syntax is only available for inter-column/row */
if (arch_direct.type(direct) != e_direct_type::INTER_COLUMN && arch_direct.type(direct) != e_direct_type::INTER_ROW) {
if (arch_direct.type(direct) != e_direct_type::INTER_COLUMN &&
arch_direct.type(direct) != e_direct_type::INTER_ROW) {
continue;
}

9
openfpga/src/tile_direct/build_tile_direct.cpp
View File

@ -329,7 +329,8 @@ static vtr::Point<size_t> find_inter_direct_destination_coordinate(
if (e_direct_type::INTER_COLUMN == arch_direct.type(arch_direct_id)) {
next_col_row_coords.push_back(vtr::Point<size_t>(ix, iy));
} else {
VTR_ASSERT(e_direct_type::INTER_ROW == arch_direct.type(arch_direct_id));
VTR_ASSERT(e_direct_type::INTER_ROW ==
arch_direct.type(arch_direct_id));
/* For cross-row connection, our search space is flipped */
next_col_row_coords.push_back(vtr::Point<size_t>(iy, ix));
}
@ -804,11 +805,13 @@ TileDirect build_device_tile_direct(const DeviceContext& device_ctx,
exit(1);
}
/* Build from original VPR arch definition */
if (e_direct_type::INNER_COLUMN_OR_ROW == arch_direct.type(arch_direct_id)) {
if (e_direct_type::INNER_COLUMN_OR_ROW ==
arch_direct.type(arch_direct_id)) {
build_inner_column_row_tile_direct(tile_direct,
device_ctx.arch->Directs[idirect],
device_ctx, arch_direct_id, verbose);
/* Skip those direct connections which belong part of a connection block */
/* Skip those direct connections which belong part of a connection block
*/
}
/* Build from OpenFPGA arch definition */
build_inter_column_row_tile_direct(