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[Flow] Add an example simulation settings for a 4-clock FPGA fabric

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tangxifan 2021-01-13 17:29:39 -07:00
parent 2b959290e9
commit 923f3a3401
1 changed files with 49 additions and 0 deletions
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openfpga_flow/openfpga_simulation_settings/fixed_4clock_sim_openfpga.xml Normal file
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<!-- Simulation Setting for OpenFPGA framework
This file will use automatic inference for any settings
including:
- auto select the number of simulation cycles
- auto select the simulation clock frequency from VPR results
-->
<openfpga_simulation_setting>
<clock_setting>
<!-- The frequency defined in the operating line will be
the default operating clock frequency for all the clocks
define specific frequency using <clock> line will overwrite the default value
Note that the clock name must match clock port definition in OpenFPGA architecture XML!!!
-->
<operating frequency="50e6" num_cycles="100" slack="0.2">
<clock name="clk[0:0]" frequency="10e6"/>
<clock name="clk[1:1]" frequency="20e6"/>
<clock name="clk[2:2]" frequency="30e6"/>
<clock name="clk[3:3]" frequency="40e6"/>
</operating>
<programming frequency="100e6"/>
</clock_setting>
<simulator_option>
<operating_condition temperature="25"/>
<output_log verbose="false" captab="false"/>
<accuracy type="abs" value="1e-13"/>
<runtime fast_simulation="true"/>
</simulator_option>
<monte_carlo num_simulation_points="2"/>
<measurement_setting>
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
</slew>
<delay>
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay>
</measurement_setting>
<stimulus>
<clock>
<rise slew_type="abs" slew_time="20e-12" />
<fall slew_type="abs" slew_time="20e-12" />
</clock>
<input>
<rise slew_type="abs" slew_time="25e-12" />
<fall slew_type="abs" slew_time="25e-12" />
</input>
</stimulus>
</openfpga_simulation_setting>