[test] now use local clock as one of the pins in a clock bus, but connected to global routing
This commit is contained in:
tangxifan
parent
26f71656de
commit
9222d085cd
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@ -29,6 +29,7 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f
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- registerable\_io: If I/Os are registerable (can be either combinational or sequential)
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- registerable\_io: If I/Os are registerable (can be either combinational or sequential)
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- stdcell: If circuit designs are built with standard cells only
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- stdcell: If circuit designs are built with standard cells only
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- tree\_mux: If routing multiplexers are built with a tree-like structure
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- tree\_mux: If routing multiplexers are built with a tree-like structure
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- localClkGen: The clock signal of CLB can be generated by internal programmable resources
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- <feature_size>: The technology node which the delay numbers are extracted from.
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- <feature_size>: The technology node which the delay numbers are extracted from.
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- powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating.
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- powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating.
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- GlobalTile<Int>Clk<Pin>: How many clocks are defined through global ports from physical tiles.
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- GlobalTile<Int>Clk<Pin>: How many clocks are defined through global ports from physical tiles.
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@ -0,0 +1,255 @@
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<?xml version="1.0"?>
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<!-- Architecture annotation for OpenFPGA framework
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This annotation supports the k6_N10_40nm.xml
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- General purpose logic block
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- K = 6, N = 10, I = 40
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- Single mode
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- Routing architecture
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- L = 4, fc_in = 0.15, fc_out = 0.1
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-->
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<openfpga_architecture>
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<technology_library>
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<device_library>
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<device_model name="logic" type="transistor">
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<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="0.9" pn_ratio="2"/>
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<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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</device_model>
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<device_model name="io" type="transistor">
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<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="2.5" pn_ratio="3"/>
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<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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</device_model>
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</device_library>
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<variation_library>
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<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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</variation_library>
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</technology_library>
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<circuit_library>
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<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
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<design_technology type="cmos" topology="OR"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="a" size="1"/>
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<port type="input" prefix="b" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="a b" out_port="out">
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10e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="a b" out_port="out">
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10e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
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<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="input" prefix="sel" lib_name="S" size="1"/>
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<port type="input" prefix="selb" lib_name="SI" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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<delay_matrix type="rise" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
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<!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="0" C="0" num_level="1"/>
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<!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="tap_buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
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<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="tap_buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="MULTI_MODE_DFFRQ" prefix="MULTI_MODE_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="R" lib_name="RST" size="1" default_val="0"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="C" lib_name="CK" size="1" default_val="0"/>
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<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="0"/>
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</circuit_model>
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<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
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<lut_input_buffer exist="true" circuit_model_name="buf4"/>
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<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="OR2"/>
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<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
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<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
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<port type="sram" prefix="sram" size="16"/>
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<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
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<port type="input" prefix="D" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="output" prefix="QN" size="1"/>
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<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
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</circuit_model>
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<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
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<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
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<port type="input" prefix="outpad" lib_name="A" size="1"/>
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<port type="output" prefix="inpad" lib_name="Y" size="1"/>
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</circuit_model>
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</circuit_library>
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<configuration_protocol>
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<organization type="scan_chain" circuit_model_name="DFFR"/>
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</configuration_protocol>
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<connection_block>
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<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
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</connection_block>
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<switch_block>
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<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
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</switch_block>
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<routing_segment>
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<segment name="L4" circuit_model_name="chan_segment"/>
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</routing_segment>
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<tile_annotations>
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<global_port name="op_clk" tile_port="clb.clk[1]" is_clock="true" default_val="0">
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<tile name="clb" port="clk[1]"/>
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</global_port>
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<global_port name="op_reset" is_reset="true" default_val="0">
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<tile name="clb" port="reset"/>
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</global_port>
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</tile_annotations>
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<pb_type_annotations>
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<!-- physical pb_type binding in complex block IO -->
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<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
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<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
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<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
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<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
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<!-- End physical pb_type binding in complex block IO -->
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<!-- physical pb_type binding in complex block CLB -->
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<!-- physical mode will be the default mode if not specified -->
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<pb_type name="clb">
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<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
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<interconnect name="crossbar" circuit_model_name="mux_2level"/>
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</pb_type>
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<pb_type name="clb.fle" physical_mode_name="physical"/>
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<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
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<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="MULTI_MODE_DFFRQ" mode_bits="0"/>
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<!-- Binding operating pb_type to physical pb_type -->
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<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
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<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
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<port name="in" physical_mode_port="in[0:2]"/>
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<port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
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</pb_type>
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<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0">
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<port name="clk" physical_mode_port="C"/>
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</pb_type>
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<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
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<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
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<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1">
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<port name="RN" physical_mode_port="R"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
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<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
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<port name="in" physical_mode_port="in[0:3]"/>
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<port name="out" physical_mode_port="lut4_out"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut4].ble4.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||||
|
<port name="clk" physical_mode_port="C"/>
|
||||||
|
</pb_type>
|
||||||
|
<pb_type name="clb.fle[n1_lut4].ble4.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||||
|
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||||
|
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||||
|
<port name="RN" physical_mode_port="R"/>
|
||||||
|
</pb_type>
|
||||||
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
|
</pb_type_annotations>
|
||||||
|
</openfpga_architecture>
|
||||||
|
|
@ -17,7 +17,7 @@ fpga_flow=yosys_vpr
|
||||||
|
|
||||||
[OpenFPGA_SHELL]
|
[OpenFPGA_SHELL]
|
||||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga
|
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
|
||||||
openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
|
openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -101,12 +101,10 @@
|
||||||
</equivalent_sites>
|
</equivalent_sites>
|
||||||
<input name="I" num_pins="12" equivalent="full"/>
|
<input name="I" num_pins="12" equivalent="full"/>
|
||||||
<input name="reset" num_pins="1" is_non_clock_global="true"/>
|
<input name="reset" num_pins="1" is_non_clock_global="true"/>
|
||||||
<!-- A dedicated clock for locally generated clock signals -->
|
|
||||||
<input name="lclk" num_pins="1" equivalent="none"/>
|
|
||||||
<output name="O" num_pins="8" equivalent="none"/>
|
<output name="O" num_pins="8" equivalent="none"/>
|
||||||
<clock name="clk" num_pins="1"/>
|
<clock name="clk" num_pins="2" equivalent="full"/>
|
||||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
|
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
|
||||||
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
|
<fc_override port_name="clk[1]" fc_type="frac" fc_val="0"/>
|
||||||
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
|
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
|
||||||
</fc>
|
</fc>
|
||||||
<pinlocations pattern="spread"/>
|
<pinlocations pattern="spread"/>
|
||||||
|
|
@ -277,9 +275,8 @@
|
||||||
<pb_type name="clb">
|
<pb_type name="clb">
|
||||||
<input name="I" num_pins="12" equivalent="full"/>
|
<input name="I" num_pins="12" equivalent="full"/>
|
||||||
<input name="reset" num_pins="1"/>
|
<input name="reset" num_pins="1"/>
|
||||||
<input name="lclk" num_pins="1" equivalent="none"/>
|
|
||||||
<output name="O" num_pins="8" equivalent="none"/>
|
<output name="O" num_pins="8" equivalent="none"/>
|
||||||
<clock name="clk" num_pins="1"/>
|
<clock name="clk" num_pins="2" equivalent="full"/>
|
||||||
<!-- Describe fracturable logic element.
|
<!-- Describe fracturable logic element.
|
||||||
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
|
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
|
||||||
The outputs of the fracturable logic element can be optionally registered
|
The outputs of the fracturable logic element can be optionally registered
|
||||||
|
|
@ -614,7 +611,7 @@
|
||||||
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
|
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
|
||||||
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
|
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
|
||||||
</complete>
|
</complete>
|
||||||
<complete name="clks" input="clb.clk clb.lclk" output="fle[3:0].clk">
|
<complete name="clks" input="clb.clk" output="fle[3:0].clk">
|
||||||
</complete>
|
</complete>
|
||||||
<complete name="resets" input="clb.reset" output="fle[3:0].reset">
|
<complete name="resets" input="clb.reset" output="fle[3:0].reset">
|
||||||
</complete>
|
</complete>
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue