From 921b694400e3c7d60f89a48495abf0aaea8ec08d Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Fri, 3 May 2019 10:42:35 -0600 Subject: [PATCH] Bug fix sdc breaking loop of edges outside current interconnect --- vpr7_x2p/libarchfpga/read_xml_arch_file.c | 4 ++-- .../fpga_x2p/verilog/verilog_sdc_pb_types.c | 24 +++++++++++-------- .../fpga_x2p/verilog/verilog_sdc_pb_types.h | 2 +- vpr7_x2p/vpr/SRC/pack/pb_type_graph.c | 21 +++++++++++----- 4 files changed, 32 insertions(+), 19 deletions(-) diff --git a/vpr7_x2p/libarchfpga/read_xml_arch_file.c b/vpr7_x2p/libarchfpga/read_xml_arch_file.c index 574430216..cc825709c 100644 --- a/vpr7_x2p/libarchfpga/read_xml_arch_file.c +++ b/vpr7_x2p/libarchfpga/read_xml_arch_file.c @@ -1398,7 +1398,8 @@ static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) { /* Baudouin Chauviere: SDC generation */ /* Check if property exists */ - if (Prop = FindProperty(Cur, "loop_breaker", FALSE)) { + Prop = FindProperty(Cur, "loop_breaker", FALSE); + if (NULL != Prop) { /* Check if property exists and is true */ /*if (0 == strcmp(Prop,"TRUE") || 0 == strcmp(Prop,"true")) {*/ if (0 == strcmp(Cur->name, "direct")) { @@ -1407,7 +1408,6 @@ static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) { Parent->line, Cur->name); exit(1); } - //if ( mode->interconnect[i].loop_breaker_string= my_strdup(Prop); } ezxml_set_attr(Cur, "loop_breaker", NULL); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.c index b48627494..96768ad55 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.c @@ -53,21 +53,25 @@ void sdc_dump_annotation(char* from_path, // includes the cell char* to_path, FILE* fp, - t_interconnect interconnect){ + t_pb_graph_edge* cur_edge){ + //char* min_value = NULL; + t_interconnect* cur_interconnect; float max_value = NULL; int i,j; // Find in the annotations the min and max - for (i=0; i < interconnect.num_annotations; i++) { - if (E_ANNOT_PIN_TO_PIN_DELAY == interconnect.annotations[i].type) { - for (j=0; j < interconnect.annotations[i].num_value_prop_pairs; j++) { - /* if (E_ANNOT_PIN_TO_PIN_DELAY_MIN == interconnect.annotations[i].prop[j]) { - min_value = interconnect.annotations[i].value[j]; + cur_interconnect = cur_edge->interconnect; + for (i=0; i < cur_interconnect->num_annotations; i++) { + if (E_ANNOT_PIN_TO_PIN_DELAY == cur_interconnect->annotations[i].type) { + for (j=0; j < cur_interconnect->annotations[i].num_value_prop_pairs; j++) { + /* if (E_ANNOT_PIN_TO_PIN_DELAY_MIN == interconnect->annotations[i].prop[j]) { + min_value = cur_edge->delay_min; + min_value = max_value*pow(10,9); }*/ - if(E_ANNOT_PIN_TO_PIN_DELAY_MAX == interconnect.annotations[i].prop[j]) { - max_value = atof(interconnect.annotations[i].value[j]); + if(E_ANNOT_PIN_TO_PIN_DELAY_MAX == cur_interconnect->annotations[i].prop[j]) { + max_value = cur_edge->delay_max; max_value = max_value*pow(10,9); /* converts sec in ns */ } } @@ -195,7 +199,7 @@ void dump_sdc_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, sprintf (to_path, "%s/%s", instance_name, gen_verilog_one_pb_graph_pin_full_name_in_hierarchy (des_pb_graph_pin)); // Dumping of the annotations - sdc_dump_annotation (from_path, to_path, fp, cur_interc[0]); + sdc_dump_annotation (from_path, to_path, fp, des_pb_graph_pin->input_edges[iedge]); break; case COMPLETE_INTERC: case MUX_INTERC: @@ -288,7 +292,7 @@ void dump_sdc_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, } else { // Dumping of the annotations - sdc_dump_annotation (from_path, to_path, fp, cur_interc[0]); + sdc_dump_annotation (from_path, to_path, fp, des_pb_graph_pin->input_edges[iedge]); } } break; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.h index 528e2ad5d..7f82cdf2b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.h @@ -2,7 +2,7 @@ void sdc_dump_annotation(char* from_path, // includes the cell char* to_path, FILE* fp, - t_interconnect interconnect); + t_pb_graph_edge* cur_edge); void dump_sdc_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, diff --git a/vpr7_x2p/vpr/SRC/pack/pb_type_graph.c b/vpr7_x2p/vpr/SRC/pack/pb_type_graph.c index d2fc968f2..4b59d62c2 100755 --- a/vpr7_x2p/vpr/SRC/pack/pb_type_graph.c +++ b/vpr7_x2p/vpr/SRC/pack/pb_type_graph.c @@ -89,7 +89,8 @@ static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num, int index_mode, t_pb_graph_pin*** input_pins, int num_input_ports, - int* num_input_pins); + int* num_input_pins, + t_interconnect* cur_interc); /** * Allocate memory into types and load the pb graph with interconnect edges @@ -787,7 +788,8 @@ static void alloc_and_load_mode_interconnect( index_mode, input_pb_graph_node_pins, num_input_pb_graph_node_sets, - num_input_pb_graph_node_pins); + num_input_pb_graph_node_pins, + &(mode->interconnect[i])); } /* END */ @@ -1773,7 +1775,8 @@ static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num, int index_mode, t_pb_graph_pin*** input_pins, int num_input_ports, - int* num_input_pins) { + int* num_input_pins, + t_interconnect* cur_interc) { t_token * tokens; int num_tokens; int i_tokens, cur_port_index, cur_pin_index; @@ -2065,21 +2068,27 @@ static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num, for (i_num_output_edges = 0 ; i_num_output_edges < cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].num_output_edges ; i_num_output_edges ++) { - cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE; + if (cur_interc == cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) { + cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE; + } } break; case PB_PIN_OUTPUT: for (i_num_output_edges = 0 ; i_num_output_edges < cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].num_output_edges ; i_num_output_edges ++) { - cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE; + if (cur_interc == cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) { + cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE; + } } break; case PB_PIN_CLOCK: for (i_num_output_edges = 0 ; i_num_output_edges < cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].num_output_edges ; i_num_output_edges ++) { - cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE; + if (cur_interc == cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) { + cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE; + } } break; default: