From 21d1519658cee4406f5a7a0cf208dfa51a7bb4e8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Jun 2021 16:56:28 -0600 Subject: [PATCH 1/5] [Tool] Remove signal initialization flag; Now the HDL codes will not be outputted unless specified in the option --- .../fpga_verilog/verilog_auxiliary_netlists.cpp | 6 ------ openfpga/src/fpga_verilog/verilog_constants.h | 1 - .../verilog_preconfig_top_module.cpp | 16 ++++++++++------ .../src/fpga_verilog/verilog_testbench_utils.cpp | 3 --- 4 files changed, 10 insertions(+), 16 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp index b0bacad37..85b403290 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp @@ -206,12 +206,6 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir, /* Print the title */ print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features")); - /* To enable signal initialization */ - if (true == verilog_testbench_opts.include_signal_init()) { - print_verilog_define_flag(fp, std::string(VERILOG_SIGNAL_INIT_PREPROC_FLAG), 1); - fp << std::endl; - } - /* To enable functional verfication with Icarus */ if (true == verilog_testbench_opts.support_icarus_simulator()) { print_verilog_define_flag(fp, std::string(ICARUS_SIMULATOR_FLAG), 1); diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h index 0275a40a7..e9f2f5cd8 100644 --- a/openfpga/src/fpga_verilog/verilog_constants.h +++ b/openfpga/src/fpga_verilog/verilog_constants.h @@ -7,7 +7,6 @@ constexpr char* VERILOG_NETLIST_FILE_POSTFIX = ".v"; constexpr float VERILOG_SIM_TIMESCALE = 1e-9; // Verilog Simulation time scale (minimum time unit) : 1ns constexpr char* VERILOG_TIMING_PREPROC_FLAG = "ENABLE_TIMING"; // the flag to enable timing definition during compilation -constexpr char* VERILOG_SIGNAL_INIT_PREPROC_FLAG = "ENABLE_SIGNAL_INITIALIZATION"; // the flag to enable signal initialization during compilation constexpr char* VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation constexpr char* INITIAL_SIMULATION_FLAG = "INITIAL_SIMULATION"; // the flag to enable initial functional verification constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 5b7264044..2e330fc93 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -507,12 +507,16 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager, circuit_lib, sram_model, bitstream_manager); - /* Add signal initialization */ - print_verilog_testbench_signal_initialization(fp, - std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME), - circuit_lib, - module_manager, - top_module); + /* Add signal initialization: + * Bypass writing codes to files due to the autogenerated codes are very large. + */ + if (true == options.include_signal_init()) { + print_verilog_testbench_signal_initialization(fp, + std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME), + circuit_lib, + module_manager, + top_module); + } /* Testbench ends*/ print_verilog_module_end(fp, std::string(circuit_name) + std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX)); diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 994d6f280..dfb1b2468 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -911,7 +911,6 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp, /* Add signal initialization Verilog codes */ fp << std::endl; - fp << "`ifdef " << VERILOG_SIGNAL_INIT_PREPROC_FLAG << std::endl; for (const CircuitModelId& signal_init_circuit_model : signal_init_circuit_models) { /* Find the module id corresponding to the circuit model from module graph */ ModuleId primitive_module = module_manager.find_module(circuit_lib.model_name(signal_init_circuit_model)); @@ -924,8 +923,6 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp, module_manager, top_module, primitive_module); } - - fp << "`endif" << std::endl; } } /* end namespace openfpga */ From 779437cd37f5de7111e554c5f9e9d41d825fa10e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Jun 2021 17:07:15 -0600 Subject: [PATCH 2/5] [Doc] Update documentation to remove out-of-date options related to signal_init --- .../openfpga_commands/fpga_verilog_commands.rst | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index 2a9af3b96..c41887484 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -24,14 +24,6 @@ write_fabric_verilog Output timing information to Verilog netlists for primitive modules - .. option:: --include_signal_init - - Output signal initialization to Verilog netlists for primitive modules - - .. option:: --support_icarus_simulator - - Output Verilog netlists with syntax that iVerilog simulatorcan accept - .. option:: --print_user_defined_template Output a template Verilog netlist for all the user-defined ``circuit models`` in :ref:`circuit_library`. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists @@ -118,6 +110,10 @@ write_preconfigured_fabric_wrapper Output Verilog netlists with syntax that iVerilog simulator can accept + .. option:: --include_signal_init + + Output signal initialization to Verilog testbench to smooth convergence in HDL simulation + .. option:: --verbose Show verbose log @@ -152,7 +148,6 @@ write_preconfigured_testbench Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``. - .. option:: --support_icarus_simulator Output Verilog netlists with syntax that iVerilog simulator can accept From 5364d8104fb60d056062247da27dfb381976dbab Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Jun 2021 17:07:41 -0600 Subject: [PATCH 3/5] [Tool] Add signal_init option to preconfigured fabric wrapper writer --- openfpga/src/base/openfpga_verilog.cpp | 2 ++ openfpga/src/base/openfpga_verilog_command.cpp | 3 +++ 2 files changed, 5 insertions(+) diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index 081466c06..3d853c18c 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -128,6 +128,7 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx, CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); CommandOptionId opt_default_net_type = cmd.option("default_net_type"); CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator"); + CommandOptionId opt_include_signal_init = cmd.option("include_signal_init"); CommandOptionId opt_verbose = cmd.option("verbose"); /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog @@ -139,6 +140,7 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx, options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping)); options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator)); + options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init)); options.set_print_formal_verification_top_netlist(true); if (true == cmd_context.option_enable(cmd, opt_default_net_type)) { options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type)); diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp index a890d6971..d2410bff3 100644 --- a/openfpga/src/base/openfpga_verilog_command.cpp +++ b/openfpga/src/base/openfpga_verilog_command.cpp @@ -149,6 +149,9 @@ ShellCommandId add_openfpga_write_preconfigured_fabric_wrapper_command(openfpga: /* Add an option '--support_icarus_simulator' */ shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator"); + /* add an option '--include_signal_init' */ + shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches"); + /* add an option '--verbose' */ shell_cmd.add_option("verbose", false, "enable verbose output"); From 549657e1fbbaf3dcf07e338df92c5a9fc9b9a864 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Jun 2021 17:13:36 -0600 Subject: [PATCH 4/5] [Tool] Remove out-of-date flag: INITIAL_SIMULATION from code base --- openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp | 6 ------ openfpga/src/fpga_verilog/verilog_constants.h | 1 - 2 files changed, 7 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp index 85b403290..9701a9ace 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp @@ -212,12 +212,6 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir, fp << std::endl; } - /* To enable manualy checked simulation */ - if (true == verilog_testbench_opts.print_top_testbench()) { - print_verilog_define_flag(fp, std::string(INITIAL_SIMULATION_FLAG), 1); - fp << std::endl; - } - /* To enable auto-checked simulation */ if ( (true == verilog_testbench_opts.print_preconfig_top_testbench()) || (true == verilog_testbench_opts.print_top_testbench()) ) { diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h index e9f2f5cd8..4a0ec4908 100644 --- a/openfpga/src/fpga_verilog/verilog_constants.h +++ b/openfpga/src/fpga_verilog/verilog_constants.h @@ -8,7 +8,6 @@ constexpr float VERILOG_SIM_TIMESCALE = 1e-9; // Verilog Simulation time scale ( constexpr char* VERILOG_TIMING_PREPROC_FLAG = "ENABLE_TIMING"; // the flag to enable timing definition during compilation constexpr char* VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation -constexpr char* INITIAL_SIMULATION_FLAG = "INITIAL_SIMULATION"; // the flag to enable initial functional verification constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to enable formal functional verification From 67dec810eb62dbd7374208fdb75770cb1d617e58 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Jun 2021 17:27:32 -0600 Subject: [PATCH 5/5] [Tool] Remove icarus simulator flag; Reduce the file size of preconfigured fabric wrapper by only output the necessary force/deposit HDL codes --- .../verilog_auxiliary_netlists.cpp | 6 ---- openfpga/src/fpga_verilog/verilog_constants.h | 4 --- .../verilog_preconfig_top_module.cpp | 30 +++++++++---------- 3 files changed, 14 insertions(+), 26 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp index 9701a9ace..a3ac9c580 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp @@ -206,12 +206,6 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir, /* Print the title */ print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features")); - /* To enable functional verfication with Icarus */ - if (true == verilog_testbench_opts.support_icarus_simulator()) { - print_verilog_define_flag(fp, std::string(ICARUS_SIMULATOR_FLAG), 1); - fp << std::endl; - } - /* To enable auto-checked simulation */ if ( (true == verilog_testbench_opts.print_preconfig_top_testbench()) || (true == verilog_testbench_opts.print_top_testbench()) ) { diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h index 4a0ec4908..18e23b721 100644 --- a/openfpga/src/fpga_verilog/verilog_constants.h +++ b/openfpga/src/fpga_verilog/verilog_constants.h @@ -13,10 +13,6 @@ constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to ena constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms"; -// Icarus variables and flag -constexpr char* ICARUS_SIMULATOR_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches -// End of Icarus variables and flag - constexpr char* FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME = "fabric_netlists.v"; constexpr char* TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v"; constexpr char* VERILOG_TOP_POSTFIX = "_top.v"; diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 2e330fc93..e3675428d 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -364,7 +364,8 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp, const ModuleId &top_module, const CircuitLibrary& circuit_lib, const CircuitModelId& mem_model, - const BitstreamManager &bitstream_manager) { + const BitstreamManager &bitstream_manager, + const bool& support_icarus_simulator) { /* Skip the datab port if there is only 1 output port in memory model * Currently, it assumes that the data output port is always defined while datab is optional @@ -379,21 +380,17 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp, print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----")); - print_verilog_preprocessing_flag(fp, std::string(ICARUS_SIMULATOR_FLAG)); - /* Use assign syntax for Icarus simulator */ - print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module, - bitstream_manager, - output_datab_bits); - - fp << "`else" << std::endl; - - /* Use assign syntax for Icarus simulator */ - print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module, - bitstream_manager, - output_datab_bits); - - print_verilog_endif(fp); + if (support_icarus_simulator) { + print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module, + bitstream_manager, + output_datab_bits); + } else { + /* Use deposit syntax for other simulators */ + print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module, + bitstream_manager, + output_datab_bits); + } print_verilog_comment(fp, std::string("----- End load bitstream to configuration memories -----")); } @@ -505,7 +502,8 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager, /* Assign FPGA internal SRAM/Memory ports to bitstream values */ print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module, circuit_lib, sram_model, - bitstream_manager); + bitstream_manager, + options.support_icarus_simulator()); /* Add signal initialization: * Bypass writing codes to files due to the autogenerated codes are very large.