[test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches

openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp

@@ -330,10 +330,15 @@ static void print_verilog_preconfig_top_module_force_bitstream(
     /* Drop the first block, which is the top module, it should be replaced by
      * the instance name here */
     /* Ensure that this is the module we want to drop! */
-    VTR_ASSERT(0 ==
+    VTR_LOG("Top module: '%s', Block[0]: '%s', Block[1]: '%s'\n", module_manager.module_name(top_module).c_str(), bitstream_manager.block_name(block_hierarchy[0]).c_str(), bitstream_manager.block_name(block_hierarchy[1]).c_str());
-               module_manager.module_name(top_module)
+    VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0]))
-                 .compare(bitstream_manager.block_name(block_hierarchy[0])));
+               || 0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[1])));
+    if (0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0]))) {
       block_hierarchy.erase(block_hierarchy.begin());
+    } else if (0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[1]))) {
+      block_hierarchy.erase(block_hierarchy.begin());
+      block_hierarchy.erase(block_hierarchy.begin());
+    }
     /* Build the full hierarchy path */
     std::string bit_hierarchy_path(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME);
     for (const ConfigBlockId &temp_block : block_hierarchy) {
@@ -410,10 +415,15 @@ static void print_verilog_preconfig_top_module_deposit_bitstream(
     /* Drop the first block, which is the top module, it should be replaced by
      * the instance name here */
     /* Ensure that this is the module we want to drop! */
-    VTR_ASSERT(0 ==
+    VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0]))
-               module_manager.module_name(top_module)
+               || 0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[1])));
-                 .compare(bitstream_manager.block_name(block_hierarchy[0])));
+    if (0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0]))) {
       block_hierarchy.erase(block_hierarchy.begin());
+    } else if (0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[1]))) {
+      block_hierarchy.erase(block_hierarchy.begin());
+      block_hierarchy.erase(block_hierarchy.begin());
+    }
+
     /* Build the full hierarchy path */
     std::string bit_hierarchy_path(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME);
     for (const ConfigBlockId &temp_block : block_hierarchy) {

openfpga_flow/openfpga_shell_scripts/fpga_core_example_script.openfpga

@@ -54,8 +54,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit 
+write_full_testbench ${OPENFPGA_TESTBENCH_DUT_MODULE} --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit 
-write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
+write_preconfigured_fabric_wrapper ${OPENFPGA_TESTBENCH_DUT_MODULE} --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
 write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping 
 
 # Write the SDC files for PnR backend

openfpga_flow/openfpga_shell_scripts/write_full_testbench_fpga_core_example_script.openfpga

@@ -54,7 +54,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --explicit_port_mapping --bitstream fabric_bitstream.bit ${OPENFPGA_FAST_CONFIGURATION}
+write_full_testbench ${OPENFPGA_TESTBENCH_DUT_MODULE} --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --explicit_port_mapping --bitstream fabric_bitstream.bit ${OPENFPGA_FAST_CONFIGURATION}
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here

openfpga_flow/regression_test_scripts/basic_reg_test.sh

@@ -18,8 +18,10 @@ run-task basic_tests/source_command/source_file $@
 echo -e "Testing testbenches using fpga core wrapper"
 run-task basic_tests/full_testbench/fpga_core_wrapper $@
 run-task basic_tests/full_testbench/fpga_core_wrapper_naming_rules $@
+run-task basic_tests/full_testbench/fpga_core_wrapper_naming_rules_use_core_tb $@
 run-task basic_tests/preconfig_testbench/fpga_core_wrapper $@
 run-task basic_tests/preconfig_testbench/fpga_core_wrapper_naming_rules $@
+run-task basic_tests/preconfig_testbench/fpga_core_wrapper_naming_rules_use_core_tb $@
 
 echo -e "Testing configuration chain of a K4N4 FPGA";
 run-task basic_tests/full_testbench/configuration_chain $@

openfpga_flow/tasks/basic_tests/full_testbench/fpga_core_wrapper/config/task.conf

@@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
 openfpga_vpr_device_layout=
 openfpga_fast_configuration=
 openfpga_wrapper_io_naming_rules=
+openfpga_testbench_dut_module=
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml

openfpga_flow/tasks/basic_tests/full_testbench/fpga_core_wrapper_naming_rules_use_core_tb/config/task.conf

@@ -0,0 +1,44 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_fpga_core_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=
+openfpga_fast_configuration=
+openfpga_wrapper_io_naming_rules=--io_naming ${PATH:TASK_DIR}/config/wrapper_io_naming.xml
+openfpga_testbench_dut_module=--dut_module fpga_core
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+bench1_top = or2
+
+bench2_top = and2_latch
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=

openfpga_flow/tasks/basic_tests/full_testbench/fpga_core_wrapper_naming_rules_use_core_tb/config/wrapper_io_naming.xml

@@ -0,0 +1,11 @@
+<ports>
+  <port top_name="pclk" core_name="prog_clk"/> 
+  <port top_name="top_io[0:7]" core_name="gfpga_pad_GPIO_PAD[0:7]"/> 
+  <port top_name="right_ioA[0:3]" core_name="gfpga_pad_GPIO_PAD[8:11]"/> 
+  <port top_name="right_ioB[0:3]" core_name="gfpga_pad_GPIO_PAD[12:15]"/> 
+  <port top_name="bottom_io[0:7]" core_name="gfpga_pad_GPIO_PAD[16:23]"/> 
+  <port top_name="left_io[0:7]" core_name="gfpga_pad_GPIO_PAD[24:31]"/> 
+  <port top_name="config_head" core_name="ccff_head"/> 
+  <port top_name="config_tail" core_name="ccff_tail"/> 
+  <port top_name="pvt_sensor" is_dummy="true" direction="input"/>
+</ports>

openfpga_flow/tasks/basic_tests/preconfig_testbench/fpga_core_wrapper/config/task.conf

@@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 openfpga_wrapper_io_naming_rules=
+openfpga_testbench_dut_module=
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml

openfpga_flow/tasks/basic_tests/preconfig_testbench/fpga_core_wrapper_naming_rules/config/task.conf

@@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 openfpga_wrapper_io_naming_rules=--io_naming ${PATH:TASK_DIR}/config/wrapper_io_naming.xml
+openfpga_testbench_dut_module=
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml

openfpga_flow/tasks/basic_tests/preconfig_testbench/fpga_core_wrapper_naming_rules_use_core_tb/config/task.conf

@@ -0,0 +1,43 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fpga_core_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_wrapper_io_naming_rules=--io_naming ${PATH:TASK_DIR}/config/wrapper_io_naming.xml
+openfpga_testbench_dut_module= --dut_module fpga_core
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+bench1_top = or2
+
+bench2_top = and2_latch
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

openfpga_flow/tasks/basic_tests/preconfig_testbench/fpga_core_wrapper_naming_rules_use_core_tb/config/wrapper_io_naming.xml

@@ -0,0 +1,11 @@
+<ports>
+  <port top_name="pclk" core_name="prog_clk"/> 
+  <port top_name="top_io[0:7]" core_name="gfpga_pad_GPIO_PAD[0:7]"/> 
+  <port top_name="right_ioA[0:3]" core_name="gfpga_pad_GPIO_PAD[8:11]"/> 
+  <port top_name="right_ioB[0:3]" core_name="gfpga_pad_GPIO_PAD[12:15]"/> 
+  <port top_name="bottom_io[0:7]" core_name="gfpga_pad_GPIO_PAD[16:23]"/> 
+  <port top_name="left_io[0:7]" core_name="gfpga_pad_GPIO_PAD[24:31]"/> 
+  <port top_name="config_head" core_name="ccff_head"/> 
+  <port top_name="config_tail" core_name="ccff_tail"/> 
+  <port top_name="pvt_sensor" is_dummy="true" direction="input"/>
+</ports>