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clean up and reorganize XML about technology library

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tangxifan 2020-01-17 09:24:58 -07:00
parent 5c69f57559
commit 910c69d7e5
1 changed files with 18 additions and 14 deletions
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32
libopenfpga/libarchopenfpga/arch/sample_arch.xml
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@ -10,21 +10,25 @@
<openfpga_architecture> <openfpga_architecture>
<technology> <technology>
<library type="academia" corner="TOP_TT" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/> <library type="academia" corner="TOP_TT" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<logic_transistors pn_ratio="2" model_ref="M" vdd="0.9"> <transistors name="logic" type="logic" pn_ratio="2" model_ref="M" vdd="0.9">
<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/> <nmos model_name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/> <pmos model_name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
<variation abs_variation="0.1" num_sigma="3"/> </transistors>
</logic_transistors> <transistors name="io" type="io" pn_ratio="3" model_ref="M" vdd="2.5">
<io_transistors pn_ratio="2" model_ref="M" vdd="2.5"> <nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
<nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/> <pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
<pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/> </transistors>
</io_transistors> <rram_devices>
<rram model_name="rram_mem" rlrs="1e4" rhrs="1e5"> <rram model_name="mem_rram" rlrs="1e4" rhrs="1e5" variation="mem_rram_var">
<variation abs_variation="0.1" num_sigma="3"/> <rram model_name="logic_rram" rlrs="5e3" rhrs="20e6" variation="logic_rram_var">
</rram> </rram_devices>
<rram model_name="rram_logic" rlrs="5e3" rhrs="20e6">
<variation abs_variation="0.1" num_sigma="3"/>
</rram> </rram>
<device_variation>
<variation name="logic_transistor_var" abs_variation="0.1" num_sigma="3"/>
<variation name="io_transistor_var" abs_variation="0.1" num_sigma="3"/>
<variation name="mem_rram_var" abs_variation="0.1" num_sigma="3"/>
<variation name="logic_rram_var" abs_variation="0.1" num_sigma="3"/>
</device_variation>
</technology> </technology>
<circuit_library> <circuit_library>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true"> <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">