massively deploy disable_timing for configure ports in CI

openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga

@@ -55,6 +55,9 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE
 #  - Turn on every options here
 write_pnr_sdc --file ./SDC
 
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
 # Write the SDC to run timing analysis for a mapped FPGA fabric
 write_analysis_sdc --file ./SDC_analysis
 

openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga

@@ -55,6 +55,9 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE
 #  - Turn on every options here
 write_pnr_sdc --file ./SDC
 
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
 # Write the SDC to run timing analysis for a mapped FPGA fabric
 write_analysis_sdc --file ./SDC_analysis
 

openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga

@@ -29,6 +29,9 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc
 #  - Turn on every options here
 write_pnr_sdc --file ./SDC
 
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
 # Finish and exit OpenFPGA
 exit
 

openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga

@@ -55,6 +55,9 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE
 #  - Turn on every options here
 write_pnr_sdc --file ./SDC
 
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
 # Write the SDC to run timing analysis for a mapped FPGA fabric
 write_analysis_sdc --file ./SDC_analysis
 

openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga

@@ -59,6 +59,9 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ./${REFEREN
 #  - Turn on every options here
 write_pnr_sdc --file ./SDC
 
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
 # Write the SDC to run timing analysis for a mapped FPGA fabric
 write_analysis_sdc --file ./SDC_analysis
 

openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga

@@ -55,6 +55,9 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE
 #  - Turn on every options here
 write_pnr_sdc --time_unit ps --file ./SDC
 
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
 # Write the SDC to run timing analysis for a mapped FPGA fabric
 write_analysis_sdc --time_unit ps --file ./SDC_analysis