From 910be3cadb0197d9254d1c1b0bfc6b0210ae6fb9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 14 May 2020 17:23:58 -0600 Subject: [PATCH] massively deploy disable_timing for configure ports in CI --- .../duplicated_grid_pin_example_script.openfpga | 3 +++ .../flatten_routing_example_script.openfpga | 3 +++ .../generate_fabric_example_script.openfpga | 3 +++ .../implicit_verilog_example_script.openfpga | 3 +++ .../OpenFPGAShellScripts/mcnc_example_script.openfpga | 3 +++ .../OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga | 3 +++ 6 files changed, 18 insertions(+) diff --git a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga index 1ccd8418d..f1dc80820 100644 --- a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga @@ -55,6 +55,9 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE # - Turn on every options here write_pnr_sdc --file ./SDC +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + # Write the SDC to run timing analysis for a mapped FPGA fabric write_analysis_sdc --file ./SDC_analysis diff --git a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga index 529fc19ae..88be8a878 100644 --- a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga @@ -55,6 +55,9 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE # - Turn on every options here write_pnr_sdc --file ./SDC +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + # Write the SDC to run timing analysis for a mapped FPGA fabric write_analysis_sdc --file ./SDC_analysis diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga index 6514f36b4..ff40f4c76 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga @@ -29,6 +29,9 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc # - Turn on every options here write_pnr_sdc --file ./SDC +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + # Finish and exit OpenFPGA exit diff --git a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga index aa4ea30ad..579e113a9 100644 --- a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga @@ -55,6 +55,9 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE # - Turn on every options here write_pnr_sdc --file ./SDC +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + # Write the SDC to run timing analysis for a mapped FPGA fabric write_analysis_sdc --file ./SDC_analysis diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga index 71d3ee294..3293979ea 100644 --- a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga @@ -59,6 +59,9 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ./${REFEREN # - Turn on every options here write_pnr_sdc --file ./SDC +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + # Write the SDC to run timing analysis for a mapped FPGA fabric write_analysis_sdc --file ./SDC_analysis diff --git a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga index 39c4d1c70..b4b6ff5ef 100644 --- a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga @@ -55,6 +55,9 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE # - Turn on every options here write_pnr_sdc --time_unit ps --file ./SDC +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + # Write the SDC to run timing analysis for a mapped FPGA fabric write_analysis_sdc --time_unit ps --file ./SDC_analysis