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[Architecture] Use strict latch Verilog HDL in frame-based procotol

This commit is contained in:
tangxifan 2020-09-23 17:58:13 -06:00
parent 645db17168
commit 906191e931
12 changed files with 16 additions and 25 deletions
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6
openfpga_flow/VerilogNetlists/config_latch.v
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@ -2,14 +2,12 @@
// Design Name : config_latch
// File Name : config_latch.v
// Function : A Configurable Latch where data storage
// can be updated at rising clock edge
// when wl is enabled
// can be updated when wl is enabled
// Reset is active high
// Coder : Xifan TANG
//-----------------------------------------------------
module config_latch (
input reset, // Reset input
input clk, // Clock Input
input wl, // Data Enable
input bl, // Data Input
output Q, // Q output
@ -19,7 +17,7 @@ module config_latch (
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge clk or posedge reset) begin
always @ ( posedge reset) begin
if (reset) begin
q_reg <= 1'b0;
end else if (1'b1 == wl) begin

6
openfpga_flow/VerilogNetlists/config_latch_neg_rst.v
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@ -2,14 +2,12 @@
// Design Name : config_latch
// File Name : config_latch.v
// Function : A Configurable Latch where data storage
// can be updated at rising clock edge
// when wl is enabled
// can be updated when wl is enabled
// Reset is active low
// Coder : Xifan TANG
//-----------------------------------------------------
module config_latch (
input resetb, // Reset input
input clk, // Clock Input
input wl, // Data Enable
input bl, // Data Input
output Q, // Q output
@ -19,7 +17,7 @@ module config_latch (
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge clk or posedge resetb) begin
always @ ( posedge resetb) begin
if (~resetb) begin
q_reg <= 1'b0;
end else if (1'b1 == wl) begin

19
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml → openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml
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@ -145,28 +145,31 @@
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="16"/>
</circuit_model>
<circuit_model type="sram" name="sram_blwl" prefix="sram_blwl" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFF_EN" prefix="DFF_EN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/DFF_EN.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/DFF_EN.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" size="1"/>
<port type="wl" prefix="wl" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="output" prefix="outb" size="1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QB" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sram_blwl" default_val="1"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="DFF_EN" default_val="1"/>
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="frame_based" circuit_model_name="sram_blwl"/>
<organization type="frame_based" circuit_model_name="DFF_EN"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>

1
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
View File

@ -155,7 +155,6 @@
<port type="wl" prefix="wl" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>

1
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml
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@ -155,7 +155,6 @@
<port type="wl" prefix="wl" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>

1
openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml
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@ -161,7 +161,6 @@
<port type="wl" prefix="wl" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>

1
openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml
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@ -155,7 +155,6 @@
<port type="wl" prefix="wl" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>

1
openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml
View File

@ -155,7 +155,6 @@
<port type="wl" prefix="wl" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>

1
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml
View File

@ -173,7 +173,6 @@
<port type="wl" prefix="wl" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>

1
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml
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@ -173,7 +173,6 @@
<port type="wl" prefix="wl" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>

1
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
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@ -173,7 +173,6 @@
<port type="wl" prefix="wl" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>

2
openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_sram/config/task.conf → openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf
View File

@ -17,7 +17,7 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
[ARCHITECTURES]