[Tool] Replace option '--support_icarus_simulator' with a new one '--preload_bitstream <string>'

openfpga/src/base/openfpga_verilog.cpp

@@ -79,6 +79,7 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
   CommandOptionId opt_default_net_type = cmd.option("default_net_type");
   CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
+  CommandOptionId opt_embed_bitstream = cmd.option("embed_bitstream");
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@@ -97,6 +98,10 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx,
     options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type));
   }
 
+  if (true == cmd_context.option_enable(cmd, opt_embed_bitstream)) {
+    options.set_embedded_bitstream_hdl_type(cmd_context.option_value(cmd, opt_embed_bitstream));
+  }
+
   /* If pin constraints are enabled by command options, read the file */
   PinConstraints pin_constraints;
   if (true == cmd_context.option_enable(cmd, opt_pcf)) {
@@ -130,7 +135,6 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
   CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
   CommandOptionId opt_default_net_type = cmd.option("default_net_type");
-  CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
   CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
   CommandOptionId opt_verbose = cmd.option("verbose");
 
@@ -142,7 +146,6 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
   options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
   options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
   options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
-  options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
   options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
   options.set_print_formal_verification_top_netlist(true);
   if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
@@ -178,7 +181,6 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
   CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path");
   CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
-  CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
   CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
   CommandOptionId opt_default_net_type = cmd.option("default_net_type");
   CommandOptionId opt_verbose = cmd.option("verbose");
@@ -190,7 +192,6 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
   options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
   options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
   options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
-  options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
   options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
   options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
   options.set_print_preconfig_top_testbench(true);

openfpga/src/base/openfpga_verilog_command.cpp

@@ -146,8 +146,9 @@ ShellCommandId add_openfpga_write_preconfigured_fabric_wrapper_command(openfpga:
   CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'");
   shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING);
 
-  /* Add an option '--support_icarus_simulator' */
+  /* Add an option '--embed_bitstream' */
-  shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator");
+  CommandOptionId embed_bitstream_opt = shell_cmd.add_option("embed_bitstream", false, "Embed bitstream to the Verilog wrapper netlist; This may cause a large netlist file size");
+  shell_cmd.set_option_require_value(embed_bitstream_opt, openfpga::OPT_STRING);
 
   /* add an option '--include_signal_init' */
   shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches");
@@ -195,9 +196,6 @@ ShellCommandId add_openfpga_write_preconfigured_testbench_command(openfpga::Shel
   CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
   shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
 
-  /* Add an option '--support_icarus_simulator' */
-  shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator");
-
   /* Add an option '--explicit_port_mapping' */
   shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
 

openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp

@@ -365,7 +365,7 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp,
                                                        const CircuitLibrary& circuit_lib,
                                                        const CircuitModelId& mem_model,
                                                        const BitstreamManager &bitstream_manager,
-                                                       const bool& support_icarus_simulator) {
+                                                       const e_embedded_bitstream_hdl_type& embedded_bitstream_hdl_type) {
 
   /* Skip the datab port if there is only 1 output port in memory model
    * Currently, it assumes that the data output port is always defined while datab is optional
@@ -381,12 +381,13 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp,
   print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----"));
 
   /* Use assign syntax for Icarus simulator */
-  if (support_icarus_simulator) {
+  if (EMBEDDED_BITSTREAM_HDL_IVERILOG == embedded_bitstream_hdl_type) {
     print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module,
                                                         bitstream_manager,
                                                         output_datab_bits);
   } else {
     /* Use deposit syntax for other simulators */
+    VTR_ASSERT(EMBEDDED_BITSTREAM_HDL_MODELSIM == embedded_bitstream_hdl_type);
     print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module,
                                                          bitstream_manager,
                                                          output_datab_bits);
@@ -499,11 +500,11 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
   CircuitModelId sram_model = config_protocol.memory_model();  
   VTR_ASSERT(true == circuit_lib.valid_model_id(sram_model));
 
-  /* Assign FPGA internal SRAM/Memory ports to bitstream values */
+  /* Assign FPGA internal SRAM/Memory ports to bitstream values, only output when needed */
   print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module,
                                                     circuit_lib, sram_model, 
                                                     bitstream_manager,
-                                                    options.support_icarus_simulator());
+                                                    options.embedded_bitstream_hdl_type());
 
   /* Add signal initialization: 
    * Bypass writing codes to files due to the autogenerated codes are very large.

openfpga/src/fpga_verilog/verilog_testbench_options.cpp

@@ -21,9 +21,9 @@ VerilogTestbenchOption::VerilogTestbenchOption() {
   print_top_testbench_ = false;
   simulation_ini_path_.clear();
   explicit_port_mapping_ = false;
-  support_icarus_simulator_ = false;
   include_signal_init_ = false;
   default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE;
+  embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM;
   time_unit_ = 1E-3;
   verbose_output_ = false;
 }
@@ -75,10 +75,6 @@ bool VerilogTestbenchOption::include_signal_init() const {
   return include_signal_init_;
 }
 
-bool VerilogTestbenchOption::support_icarus_simulator() const {
-  return support_icarus_simulator_;
-}
-
 e_verilog_default_net_type VerilogTestbenchOption::default_net_type() const {
   return default_net_type_;
 }
@@ -87,6 +83,10 @@ float VerilogTestbenchOption::time_unit() const {
   return time_unit_;
 }
 
+e_embedded_bitstream_hdl_type VerilogTestbenchOption::embedded_bitstream_hdl_type() const {
+  return embedded_bitstream_hdl_type_; 
+}
+
 bool VerilogTestbenchOption::verbose_output() const {
   return verbose_output_;
 }
@@ -147,10 +147,6 @@ void VerilogTestbenchOption::set_include_signal_init(const bool& enabled) {
   include_signal_init_ = enabled;
 }
 
-void VerilogTestbenchOption::set_support_icarus_simulator(const bool& enabled) {
-  support_icarus_simulator_ = enabled;
-}
-
 void VerilogTestbenchOption::set_default_net_type(const std::string& default_net_type) {
   /* Decode from net type string */;
   if (default_net_type == std::string(VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_NONE])) {
@@ -165,6 +161,23 @@ void VerilogTestbenchOption::set_default_net_type(const std::string& default_net
   }
 }
 
+void VerilogTestbenchOption::set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type) {
+  /* Decode from HDL type string */;
+  if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[NUM_EMBEDDED_BITSTREAM_HDL_TYPES])) {
+    embedded_bitstream_hdl_type_ = NUM_EMBEDDED_BITSTREAM_HDL_TYPES;
+  } else if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_IVERILOG])) {
+    embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_IVERILOG;
+  } else if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_MODELSIM])) {
+    embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM;
+  } else {
+    VTR_LOG_WARN("Invalid embedded bitstream type: '%s'! Expect ['%s'|'%s'|'%s']\n",
+                 embedded_bitstream_hdl_type.c_str(),
+                 EMBEDDED_BITSTREAM_HDL_TYPE_STRING[NUM_EMBEDDED_BITSTREAM_HDL_TYPES],
+                 EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_IVERILOG],
+                 EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_MODELSIM]);
+  }
+}
+
 void VerilogTestbenchOption::set_time_unit(const float& time_unit) {
   time_unit_ = time_unit;
 }

openfpga/src/fpga_verilog/verilog_testbench_options.h

@@ -10,6 +10,15 @@
 /* Begin namespace openfpga */
 namespace openfpga {
 
+/* Embedded bitstream code style */
+enum e_embedded_bitstream_hdl_type {
+  EMBEDDED_BITSTREAM_HDL_IVERILOG,
+  EMBEDDED_BITSTREAM_HDL_MODELSIM,
+  NUM_EMBEDDED_BITSTREAM_HDL_TYPES
+};
+
+constexpr std::array<const char*, NUM_EMBEDDED_BITSTREAM_HDL_TYPES + 1> EMBEDDED_BITSTREAM_HDL_TYPE_STRING = {{"iverilog", "modelsim", "none"}}; //String versions of default net types
+
 /********************************************************************
  * Options for Verilog Testbench generator
  * Typicall usage:
@@ -34,8 +43,8 @@ class VerilogTestbenchOption {
     std::string simulation_ini_path() const;
     bool explicit_port_mapping() const;
     bool include_signal_init() const;
-    bool support_icarus_simulator() const;
     e_verilog_default_net_type default_net_type() const;
+    e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type() const;
     float time_unit() const;
     bool verbose_output() const;
   public: /* Public validator */
@@ -60,9 +69,9 @@ class VerilogTestbenchOption {
     void set_print_simulation_ini(const std::string& simulation_ini_path);
     void set_explicit_port_mapping(const bool& enabled);
     void set_include_signal_init(const bool& enabled);
-    void set_support_icarus_simulator(const bool& enabled);
     void set_default_net_type(const std::string& default_net_type);
     void set_time_unit(const float& time_unit);
+    void set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type);
     void set_verbose_output(const bool& enabled);
   private: /* Internal Data */
     std::string output_directory_;
@@ -75,9 +84,9 @@ class VerilogTestbenchOption {
     /* Print simulation ini is enabled only when the path is not empty */
     std::string simulation_ini_path_;
     bool explicit_port_mapping_;
-    bool support_icarus_simulator_;
     bool include_signal_init_;
     e_verilog_default_net_type default_net_type_;
+    e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type_;
     float time_unit_;
     bool verbose_output_;
 };