diff --git a/.github/workflows/fpga_verilog_reg_test.sh b/.github/workflows/fpga_verilog_reg_test.sh index 7fcf75b3e..a866b7bfc 100755 --- a/.github/workflows/fpga_verilog_reg_test.sh +++ b/.github/workflows/fpga_verilog_reg_test.sh @@ -13,6 +13,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mo echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 "; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs +echo -e "Testing Verilog generation for LUTs: native fracturable LUT4 "; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_native_lut4 --debug --show_thread_logs + echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs diff --git a/docs/source/manual/arch_lang/circuit_model_examples.rst b/docs/source/manual/arch_lang/circuit_model_examples.rst index 31391993f..b9af6be37 100644 --- a/docs/source/manual/arch_lang/circuit_model_examples.rst +++ b/docs/source/manual/arch_lang/circuit_model_examples.rst @@ -724,7 +724,15 @@ Template - ``circuit_model_name=""`` Specify the ``circuit_model`` that will be used to build these buffers - - ``location_map="[1|-]"`` Customize the location of buffers in intermediate stages. Users can define an integer array consisting of '1' and '-'. For example, ``-1-1-`` indicates buffer inseration to every two stages of the LUT multiplexer tree, considering a 6-input LUT. + - ``location_map="[1|-]"`` Customize the location of buffers in intermediate stages. Users can define an integer array consisting of '1' and '-'. Take the example in :numref:`fig_lut_intermediate_buffer_example`, ``-1-`` indicates buffer inseration to the second stage of the LUT multiplexer tree, considering a 3-input LUT. + +.. _fig_lut_intermediate_buffer_example: + +.. figure:: ./figures/lut_intermediate_buffer_example.svg + :scale: 80% + :alt: detailed lut composition + + An example of adding intermediate buffers to a 3-input Look-Up Table (LUT). .. note:: For a LUT, three types of ports (``input``, ``output`` and ``sram``) should be defined. If the user provides an customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. To support customizable LUTs, each type of port contain special keywords. @@ -757,40 +765,89 @@ Template Single-Output LUT ````````````````` -:numref:`fig_lut` illustrates an example of LUT modeling, which consists of input/output buffers and a transmission-gate-based tree structure. +:numref:`fig_single_lut3_example` illustrates an example of LUT modeling, which consists of input/output buffers and a transmission-gate-based tree structure. -.. _fig_lut: +.. _fig_single_lut3_example: -.. figure:: ./figures/lut.png +.. figure:: ./figures/single_lut3_example.svg :scale: 80% - :alt: Detailed LUT composition + :alt: detailed lut composition - An example of a LUT with transistor-level design parameters. + An example of a single-output 3-input LUT. The code describing this LUT is: .. code-block:: xml - + - + - + This example shows: - - A 6-input LUT which is configurable by 64 SRAM cells. - - The multiplexer inside LUT will be built with transmission gate using circuuit model ``inv1x`` + - A 3-input LUT which is configurable by 8 SRAM cells. + - The multiplexer inside LUT will be built with transmission gate using circuit model ``inv1x`` - There are no internal buffered inserted to any intermediate stage of a LUT .. _circuit_model_frac_lut_example: -Fracturable LUT -``````````````` +Standard Fracturable LUT +````````````````````````` + +:numref:`fig_frac_lut3_example` illustrates a typical example of 3-input fracturable LUT modeling, which consists of input/output buffers and a transmission-gate-based tree structure. + +.. _fig_frac_lut3_example: + +.. figure:: ./figures/frac_lut3_example.svg + :scale: 80% + :alt: detailed lut composition + + An example of a fracturable 3-input LUT. + +The code describing this LUT is: + +.. code-block:: xml + + + + + + + + + + + + + + + +This example shows: + - Fracturable 3-input LUT which is configurable by 9 SRAM cells. + - There is a SRAM cell to switch the operating mode of this LUT, configured by a configuration-chain flip-flop ``ccff`` + - The last input ``in[2]`` of LUT will be tri-stated in dual-LUT2 mode. + - An 2-input OR gate will be wired to the last input ``in[2]`` to tri-state the input. The mode-select SRAM will be wired to an input of the OR gate. + It means that when the mode-selection bit is '1', the LUT will operate in dual-LUT5 mode. + - There will be two outputs wired to the 5th stage of routing multiplexer (the outputs of dual 5-input LUTs) + - By default, the mode-selection configuration bit will be '1', indicating that by default the LUT will operate in dual-LUT2 mode. + +:numref:`fig_std_frac_lut` illustrates the detailed schematic of a standard fracturable 6-input LUT, where the 5th and 6th inputs can be pull up/down to a fixed logic value to enable LUT4 and LUT5 outputs. + +.. _fig_std_frac_lut: + +.. figure:: ./figures/std_frac_lut.svg + :scale: 80% + :alt: detailed lut composition + + Detailed schematic of a standard fracturable 6-input LUT. + +The code describing this LUT is: .. code-block:: xml @@ -800,24 +857,60 @@ Fracturable LUT - - + + - + This example shows: - - Fracturable 6-input LUT which is configurable by 65 SRAM cells. - - Intermedate buffers are added to every two stages of the internal multiplexer - - There is a SRAM cell to switch the operating mode of this LUT, configured by a configuration-chain flip-flop ``ccff`` - - The last input ``in[5]`` of LUT will be tri-stated in dual-LUT5 mode. - - An 2-input OR gate will be wired to the last input ``in[5]`` to tri-state the input. The mode-select SRAM will be wired to an input of the OR gate. - It means that when the mode-selection bit is '1', the LUT will operate in dual-LUT5 mode. + - Fracturable 6-input LUT which is configurable by 66 SRAM cells. + - There are two SRAM cells to switch the operating mode of this LUT, configured by two configuration-chain flip-flops ``ccff`` + - The inputs ``in[4]`` and ``in[5]`` of LUT will be tri-stated in dual-LUT4 and dual-LUT5 modes respectively. + - An 2-input OR gate will be wired to the inputs ``in[4]`` and ``in[5]`` to tri-state them. The mode-select SRAM will be wired to an input of the OR gate. + - There will be two outputs wired to the 4th stage of routing multiplexer (the outputs of dual 4-input LUTs) - There will be two outputs wired to the 5th stage of routing multiplexer (the outputs of dual 5-input LUTs) - - By default, the mode-selection configuration bit will be '1', indicating that by default the LUT will operate in dual-LUT5 mode. + - By default, the mode-selection configuration bit will be '11', indicating that by default the LUT will operate in dual-LUT4 mode. + +Native Fracturable LUT +`````````````````````` + +:numref:`fig_native_frac_lut` illustrates the detailed schematic of a native fracturable 6-input LUT, where LUT4, LUT5 and LUT6 outputs are always active and there are no tri-state buffers. + +.. _fig_native_frac_lut: + +.. figure:: ./figures/native_frac_lut.svg + :scale: 80% + :alt: detailed lut composition + + Detailed schematic of a native fracturable 6-input LUT. + +The code describing this LUT is: + +.. code-block:: xml + + + + + + + + + + + + + + + +This example shows: + - Fracturable 6-input LUT which is configurable by 64 SRAM cells. + - There will be two outputs wired to the 4th stage of routing multiplexer (the outputs of dual 4-input LUTs) + - There will be two outputs wired to the 5th stage of routing multiplexer (the outputs of dual 5-input LUTs) + Flip-Flops ~~~~~~~~~~ diff --git a/docs/source/manual/arch_lang/figures/frac_lut3_example.svg b/docs/source/manual/arch_lang/figures/frac_lut3_example.svg new file mode 100644 index 000000000..78582dd61 --- /dev/null +++ b/docs/source/manual/arch_lang/figures/frac_lut3_example.svg @@ -0,0 +1,819 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-26 19:26:01 +0000 + + frac_lut3_example + + Legend + + + + + + + + + + + + + < + input_buffer + exist=“true + circuit_model_name=“inv1x”/> + + + + + + + < + pass_gate_logic + + circuit_model_name=“transmission_gate”/> + + + + + + + + + + < + lut_input_buffer + exist=“true + circuit_model_name=“buf2x”/> + + + + + + + + + + < + output_buffer + exist=“true” + circuit_model_name=“inv1x”/> + + + + + + + Buffers + + + + + + < + lut_input_inverter + exist=“true + circuit_model_name=“inv2x”/> + + + + + in[0] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2-input MUX + + + + + Input buffers + + + + + + + < + port type=“output” + name=“lut3_out” frac_level=“3”/> + + + + + + + < + port type=“output” + name=“lut2_out” frac_level=“2” + lut_output_mask=“0”/> + + + + + subckt + + + + in + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + + + 2 + × + + + + + + + + + + + + + + + + + 2 + × + + + + + + + + + + + + in_buf + + + + + in_inv + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + in_inv + + + + + in_buf + + + + + + + + + + + + + + + + + + + + mem_in0 + + + + + mem_in1 + + + + + out + + + + + + LUT_MUX + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Buffers + + + + + in[1] + + + + + + + + + + + + + + + + + + + + + + Buffers + + + + + in[2] + + + + + + + + + + + + + + + + + + + Configurable + Memory Bank + + + + + lut3_out + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + lut2_out + + + + + + + + + diff --git a/docs/source/manual/arch_lang/figures/lut.png b/docs/source/manual/arch_lang/figures/lut.png deleted file mode 100644 index bb9e58895..000000000 Binary files a/docs/source/manual/arch_lang/figures/lut.png and /dev/null differ diff --git a/docs/source/manual/arch_lang/figures/lut_intermediate_buffer_example.svg b/docs/source/manual/arch_lang/figures/lut_intermediate_buffer_example.svg new file mode 100644 index 000000000..ed75e259c --- /dev/null +++ b/docs/source/manual/arch_lang/figures/lut_intermediate_buffer_example.svg @@ -0,0 +1,567 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-26 19:26:01 +0000 + + lut_intermediate_buffer + + Legend + + + + + + + + + + + + + < + lut_intermediate_buffer + exist=“true circuit_model_name=“buf1x” + location_map=“ + - + 1-“ + /> + + + + + + + + + + + + location_map=“ + - + + 1 -“ + + + + + + + + + + + LUT_MUX + + + + + + + + MUX + + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Configurable + Memory Bank + + + + + out + + + + + + + + diff --git a/docs/source/manual/arch_lang/figures/native_frac_lut.svg b/docs/source/manual/arch_lang/figures/native_frac_lut.svg new file mode 100644 index 000000000..a95fb106e --- /dev/null +++ b/docs/source/manual/arch_lang/figures/native_frac_lut.svg @@ -0,0 +1,364 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-26 19:31:38 +0000 + + native_frac_lut + + Schematic + + + + + + + + + + + + + + + + + + + + + + + 4-LUT + + + + + + + + + + + + + + + + + + + 4-LUT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 4-LUT + + + + + + + + + + + + + + + + 4-LUT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + L + U + T + + + + + + + + L + U + T + + + + + + + + + + + + + + + L + U + T + + + + + + + + + + + + + + in0 + + + + + in1 + + + + + in2 + + + + + in3 + + + + + in4 + + + + + in5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + lut6_out + + + + + + lut5_out[0] + + + + + + lut5_out[1] + + + + + + lut4_out[0] + + + + + + lut4_out[1] + + + + + + + + + + + + + + + + + + + Legend + + + + + < + port type=“input” + prefix=“in” size=“6”/> + + + + + + + < + port type=“output” + prefix=“lut4_out” size=“2” + lut_frac_level=“4” lut_output_mask=“0,2”/> + + + + + + + < + port type=“output” + prefix=“lut5_out” size=“2” + lut_frac_level=“5” lut_output_mask=“0,1”/> + + + + + + + < + port type=“output” + prefix=“lut6_out” size=“1” + lut_frac_level=“6” lut_output_mask=“0”/> + + + + + diff --git a/docs/source/manual/arch_lang/figures/single_lut3_example.svg b/docs/source/manual/arch_lang/figures/single_lut3_example.svg new file mode 100644 index 000000000..6435ff602 --- /dev/null +++ b/docs/source/manual/arch_lang/figures/single_lut3_example.svg @@ -0,0 +1,769 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-26 19:26:01 +0000 + + single_lut3_example + + Legend + + + + + + + + + + + + + < + input_buffer + exist=“true + circuit_model_name=“inv1x”/> + + + + + + + < + pass_gate_logic + + circuit_model_name=“transmission_gate”/> + + + + + + + + + + < + lut_input_buffer + exist=“true + circuit_model_name=“buf2x”/> + + + + + + + + + + < + output_buffer + exist=“true” + circuit_model_name=“inv1x”/> + + + + + + + Buffers + + + + + + < + lut_input_inverter + exist=“true + circuit_model_name=“inv2x”/> + + + + + in[0] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2-input MUX + + + + + Input buffers + + + + + subckt + + + + in + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + + + 2 + × + + + + + + + + + + + + + + + + + 2 + × + + + + + + + + + + + + in_buf + + + + + in_inv + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + in_inv + + + + + in_buf + + + + + + + + + + + + + + + + + + + + mem_in0 + + + + + mem_in1 + + + + + out + + + + + + LUT_MUX + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + MUX + + + + + + + + + + + + + MUX + + + + + + + + + + + + + + + + + 1 + × + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Buffers + + + + + in[1] + + + + + + + + + + + + + + + + + + + + + + Buffers + + + + + in[2] + + + + + + + + + + + + + + + + + + + Configurable + Memory Bank + + + + + out + + + + + diff --git a/docs/source/manual/arch_lang/figures/std_frac_lut.svg b/docs/source/manual/arch_lang/figures/std_frac_lut.svg new file mode 100644 index 000000000..38a2b3e7d --- /dev/null +++ b/docs/source/manual/arch_lang/figures/std_frac_lut.svg @@ -0,0 +1,428 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-26 19:31:38 +0000 + + std_frac_lut + + Schematic + + + + + + + + + + + + + + + + + + + 4-LUT + + + + + + + + + + + + + + + + + + + 4-LUT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 4-LUT + + + + + + + + + + + + + + + + 4-LUT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + L + U + T + + + + + + + + + + + + + + + L + U + T + + + + + + + + + + + + + + in0 + + + + + in1 + + + + + in2 + + + + + in3 + + + + + in4 + + + + + in5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OR + + + + + OR + + + + + + + + + + + + + lut6_out + + + + + + lut5_out[0] + + + + + + lut5_out[1] + + + + + + lut4_out[0] + + + + + + lut4_out[1] + + + + + + + + + + + + + + + + + + + + + + + L + U + T + + + + + Legend + + + + + < + port type=“input” + prefix=“in” size=“6” + tri_state_map=“----11” circuit_model_name=“OR2”/> + + + + + + + < + port type=“output” + prefix=“lut4_out” size=“2” + lut_frac_level=“4” lut_output_mask=“0,2”/> + + + + + + + < + port type=“output” + prefix=“lut5_out” size=“2” + lut_frac_level=“5” lut_output_mask=“0,1”/> + + + + + + + < + port type=“output” + prefix=“lut6_out” size=“1” + lut_frac_level=“6” lut_output_mask=“0”/> + + + + + diff --git a/openfpga/src/fabric/build_lut_modules.cpp b/openfpga/src/fabric/build_lut_modules.cpp index 50325204b..142c2369f 100644 --- a/openfpga/src/fabric/build_lut_modules.cpp +++ b/openfpga/src/fabric/build_lut_modules.cpp @@ -73,7 +73,8 @@ void build_lut_module(ModuleManager& module_manager, VTR_ASSERT (1 == lut_input_ports.size()); VTR_ASSERT (1 <= lut_output_ports.size()); VTR_ASSERT (1 == lut_regular_sram_ports.size()); - VTR_ASSERT (1 == lut_mode_select_sram_ports.size()); + VTR_ASSERT ( (0 == lut_mode_select_sram_ports.size()) + || (1 == lut_mode_select_sram_ports.size())); } /*********************************************** @@ -268,7 +269,8 @@ void build_lut_module(ModuleManager& module_manager, } /* Sanitity check */ - if ( true == circuit_lib.is_lut_fracturable(lut_model) ) { + if ( (true == circuit_lib.is_lut_fracturable(lut_model)) + && (false == lut_mode_select_sram_ports.empty()) ) { if (mode_select_port_lsb != circuit_lib.port_size(lut_mode_select_sram_ports[0])) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Circuit model '%s' has a unmatched tri-state map '%s' implied by mode_port size='%d'!\n", diff --git a/openfpga_flow/openfpga_arch/README.md b/openfpga_flow/openfpga_arch/README.md index 2e5dede96..ba6e307ca 100644 --- a/openfpga_flow/openfpga_arch/README.md +++ b/openfpga_flow/openfpga_arch/README.md @@ -2,8 +2,9 @@ Please reveal the following architecture features in the names to help quickly spot architecture files. Note that an OpenFPGA architecture can be applied to multiple VPR architecture files. -- k: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size. -- frac: If fracturable LUT is used or not. +- k\_: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size. + * The keyword 'frac' is to specify if fracturable LUT is used or not. + * The keyword 'Native' is to specify if fracturable LUT design is a native one (without mode switch) or a standard one (with mode switch). - N: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number. - adder\_chain: If hard adder/carry chain is used inside CLBs - register\_chain: If shift register chain is used inside CLBs diff --git a/openfpga_flow/openfpga_arch/k4_fracNative_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_fracNative_N4_40nm_cc_openfpga.xml new file mode 100644 index 000000000..bb5a3acf1 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_fracNative_N4_40nm_cc_openfpga.xml @@ -0,0 +1,244 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_native_lut4/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_native_lut4/config/task.conf new file mode 100644 index 000000000..51f41156e --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_native_lut4/config/task.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_fracNative_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_fracNative_N4_tileable_40nm.xml + +[BENCHMARKS] +# +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2_or2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/vpr_arch/README.md b/openfpga_flow/vpr_arch/README.md index 99fc2075b..9ff6903e0 100644 --- a/openfpga_flow/vpr_arch/README.md +++ b/openfpga_flow/vpr_arch/README.md @@ -1,7 +1,9 @@ # Naming convention for VPR architecture files Please reveal the following architecture features in the names to help quickly spot architecture files. -- k\_: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size. The keyword 'frac' is to specify if fracturable LUT is used or not. +- k\_: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size. + * The keyword 'frac' is to specify if fracturable LUT is used or not. + * The keyword 'Native' is to specify if fracturable LUT design is a native one (without mode switch) or a standard one (with mode switch). - N: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number. - tileable: If the routing architecture is tileable or not. - adder\_chain: If hard adder/carry chain is used inside CLBs diff --git a/openfpga_flow/vpr_arch/k4_fracNative_N4_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_fracNative_N4_tileable_40nm.xml new file mode 100644 index 000000000..ebd08e86a --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_fracNative_N4_tileable_40nm.xml @@ -0,0 +1,420 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +