From 8f80cb3c24d5bb5197cc948fa377a2ccb1ae69d6 Mon Sep 17 00:00:00 2001 From: Ganesh Gore <goreganesh007@gmail.com> Date: Thu, 22 Aug 2019 17:02:12 -0600 Subject: [PATCH] Added Sample script to run blif VPR --- run_test.sh | 42 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/run_test.sh b/run_test.sh index 2acefd58d..9d85ab91b 100644 --- a/run_test.sh +++ b/run_test.sh @@ -1,16 +1,46 @@ +# python3.5 openfpga_flow/scripts/run_fpga_flow.py \ +# ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \ +# ./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \ +# --top_module s298 \ +# --power \ +# --power_tech ./openfpga_flow/tech/PTM_22nm/22nm.xml \ +# --min_route_chan_width 1.3 \ +# --vpr_fpga_verilog \ +# --vpr_fpga_verilog_dir . \ +# --vpr_fpga_x2p_rename_illegal_port \ +# --end_flow_with_test \ +# --vpr_fpga_verilog_include_icarus_simulator \ +# --vpr_fpga_verilog_formal_verification_top_netlist \ +# --vpr_fpga_verilog_include_timing \ +# --vpr_fpga_verilog_include_signal_init \ +# --vpr_fpga_verilog_print_autocheck_top_testbench + + + python3.5 openfpga_flow/scripts/run_fpga_flow.py \ ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \ -./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \ ---top_module s298 \ +./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ +--fpga_flow vpr_blif \ +--top_module test_modes \ +--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ +--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v\ --power \ ---power_tech ./openfpga_flow/tech/PTM_22nm/22nm.xml \ ---min_route_chan_width 1.3 \ +--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ +--fix_route_chan_width 300 \ --vpr_fpga_verilog \ --vpr_fpga_verilog_dir . \ --vpr_fpga_x2p_rename_illegal_port \ ---end_flow_with_test \ --vpr_fpga_verilog_include_icarus_simulator \ --vpr_fpga_verilog_formal_verification_top_netlist \ --vpr_fpga_verilog_include_timing \ --vpr_fpga_verilog_include_signal_init \ ---vpr_fpga_verilog_print_autocheck_top_testbench \ No newline at end of file +--vpr_fpga_verilog_print_autocheck_top_testbench \ +--debug \ +--vpr_fpga_bitstream_generator \ +--vpr_fpga_verilog_print_user_defined_template \ +--vpr_fpga_verilog_print_report_timing_tcl \ +--vpr_fpga_verilog_print_sdc_pnr \ +--vpr_fpga_verilog_print_sdc_analysis \ +--vpr_fpga_x2p_compact_routing_hierarchy \ +--end_flow_with_test +