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This commit is contained in:
tangxifan 2023-02-25 22:43:21 -08:00
parent 0b33650761
commit 8f0d94ba73
3 changed files with 54 additions and 39 deletions
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13
libs/libclkarchopenfpga/src/base/clock_network.cpp
View File

@ -25,7 +25,8 @@ ClockNetwork::clock_tree_range ClockNetwork::trees() const {
return vtr::make_range(tree_ids_.begin(), tree_ids_.end());
}
std::vector<ClockLevelId> ClockNetwork::levels(const ClockTreeId& tree_id) const {
std::vector<ClockLevelId> ClockNetwork::levels(
const ClockTreeId& tree_id) const {
std::vector<ClockLevelId> ret;
for (size_t ilvl = 0; ilvl < tree_depth(tree_id); ++ilvl) {
ret.push_back(ClockLevelId(ilvl));
@ -59,7 +60,9 @@ Direction ClockNetwork::spine_direction(const ClockSpineId& spine_id) const {
return Direction::DEC;
}
size_t ClockNetwork::num_tracks(const ClockTreeId& tree_id, const ClockLevelId& level, const t_rr_type& direction) const {
size_t ClockNetwork::num_tracks(const ClockTreeId& tree_id,
const ClockLevelId& level,
const t_rr_type& direction) const {
size_t num_tracks = 0;
for (ClockSpineId curr_spine : spines(tree_id)) {
if (spine_levels_[curr_spine] != size_t(level)) {
@ -383,9 +386,11 @@ bool ClockNetwork::valid_spine_switch_point_id(
return size_t(switch_point_id) < spine_switch_points_[spine_id].size();
}
bool ClockNetwork::valid_spine_start_end_points(const ClockSpineId& spine_id) const {
bool ClockNetwork::valid_spine_start_end_points(
const ClockSpineId& spine_id) const {
VTR_ASSERT(valid_spine_id(spine_id));
if ((spine_start_point(spine_id).x() != spine_end_point(spine_id).x()) && (spine_start_point(spine_id).y() != spine_end_point(spine_id).y())) {
if ((spine_start_point(spine_id).x() != spine_end_point(spine_id).x()) &&
(spine_start_point(spine_id).y() != spine_end_point(spine_id).y())) {
return false;
}
return true;

17
libs/libclkarchopenfpga/src/base/clock_network.h
View File

@ -55,8 +55,10 @@ class ClockNetwork {
std::vector<ClockSpineId> spines(const ClockTreeId& tree_id) const;
public: /* Public Accessors: Basic data query */
/* Return the number of routing tracks required by a selected clock tree at a given level and direction */
size_t num_tracks(const ClockTreeId& tree_id, const ClockLevelId& level, const t_rr_type& direction) const;
/* Return the number of routing tracks required by a selected clock tree at a
* given level and direction */
size_t num_tracks(const ClockTreeId& tree_id, const ClockLevelId& level,
const t_rr_type& direction) const;
std::string default_segment_name() const;
std::string default_switch_name() const;
std::string tree_name(const ClockTreeId& tree_id) const;
@ -65,13 +67,14 @@ class ClockNetwork {
std::string spine_name(const ClockSpineId& spine_id) const;
vtr::Point<int> spine_start_point(const ClockSpineId& spine_id) const;
vtr::Point<int> spine_end_point(const ClockSpineId& spine_id) const;
/* Identify the direction of a spine, depending on its starting and ending points
/* Identify the direction of a spine, depending on its starting and ending
* points
* - CHANX represents a horizental routing track
* - CHANY represents a vertical routing track
*/
t_rr_type spine_track_type(const ClockSpineId& spine_id) const;
/* Identify the direction of a spine, depending on its starting and ending points
* INC represents
/* Identify the direction of a spine, depending on its starting and ending
* points INC represents
* - a CHANX track goes from left to right, or
* - a CHANY track goes from bottom to top
* DEC represents
@ -135,7 +138,9 @@ class ClockNetwork {
bool valid_spine_switch_point_id(
const ClockSpineId& spine_id,
const ClockSwitchPointId& switch_point_id) const;
/* Valid starting and ending point should indicate either this is a X-direction spine or a Y-direction spine. Diagonal spine is not supported! */
/* Valid starting and ending point should indicate either this is a
* X-direction spine or a Y-direction spine. Diagonal spine is not supported!
*/
bool valid_spine_start_end_points(const ClockSpineId& spine_id) const;
private: /* Private mutators */

51
openfpga/src/annotation/append_clock_rr_graph.cpp
View File

@ -1,6 +1,7 @@
#include "append_clock_rr_graph.h"
#include "rr_graph_builder_utils.h"
#include "command_exit_codes.h"
#include "rr_graph_builder_utils.h"
#include "vtr_assert.h"
#include "vtr_geometry.h"
#include "vtr_log.h"
@ -10,19 +11,19 @@
namespace openfpga {
/********************************************************************
* Estimate the number of clock nodes to be added for a given tile and clock structure
* For each layer/level of a clock network, we need
* Estimate the number of clock nodes to be added for a given tile and clock
*structure For each layer/level of a clock network, we need
* - the clock nodes are paired in INC and DEC directions
* - the number of clock nodes depend on the width of clock tree (number of clock signals)
* - Note that some layer only need CHANX or CHANY clock nodes since clock nodes cannot make turns in the same layer.
* For instance
* - the number of clock nodes depend on the width of clock tree (number of
*clock signals)
* - Note that some layer only need CHANX or CHANY clock nodes since clock nodes
*cannot make turns in the same layer. For instance
* - Layer 0: CHANX
* - Layer 1: CHANY
* - Layer 2: CHANX
*******************************************************************/
static
size_t estimate_clock_rr_graph_num_chan_nodes(const ClockNetwork& clk_ntwk,
const t_rr_type& chan_type) {
static size_t estimate_clock_rr_graph_num_chan_nodes(
const ClockNetwork& clk_ntwk, const t_rr_type& chan_type) {
size_t num_nodes = 0;
for (auto itree : clk_ntwk.trees()) {
@ -40,8 +41,7 @@ size_t estimate_clock_rr_graph_num_chan_nodes(const ClockNetwork& clk_ntwk,
* which are in the type of CHANX and CHANY
* Note that switch blocks do not require any new nodes but new edges
*******************************************************************/
static
size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids,
static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids,
const bool& through_channel,
const ClockNetwork& clk_ntwk) {
size_t num_nodes = 0;
@ -49,9 +49,10 @@ size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids,
for (size_t iy = 0; iy < grids.height() - 1; ++iy) {
for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
vtr::Point<size_t> chanx_coord(ix, iy);
/* Bypass if the routing channel does not exist when through channels are not allowed */
if ((false == through_channel)
&& (false == is_chanx_exist(grids, chanx_coord))) {
/* Bypass if the routing channel does not exist when through channels are
* not allowed */
if ((false == through_channel) &&
(false == is_chanx_exist(grids, chanx_coord))) {
continue;
}
/* Estimate the routing tracks required by clock routing only */
@ -62,9 +63,10 @@ size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids,
for (size_t ix = 0; ix < grids.width() - 1; ++ix) {
for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
vtr::Point<size_t> chany_coord(ix, iy);
/* Bypass if the routing channel does not exist when through channel are not allowed */
if ((false == through_channel)
&& (false == is_chany_exist(grids, chany_coord))) {
/* Bypass if the routing channel does not exist when through channel are
* not allowed */
if ((false == through_channel) &&
(false == is_chany_exist(grids, chany_coord))) {
continue;
}
/* Estimate the routing tracks required by clock routing only */
@ -100,8 +102,10 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
/* Estimate the number of nodes and pre-allocate */
size_t orig_num_nodes = vpr_device_ctx.rr_graph.num_nodes();
size_t num_clock_nodes = estimate_clock_rr_graph_num_nodes(vpr_device_ctx.grid, vpr_device_ctx.arch->through_channel, clk_ntwk);
vpr_device_ctx.rr_graph_builder.reserve_nodes(num_clock_nodes + orig_num_nodes);
size_t num_clock_nodes = estimate_clock_rr_graph_num_nodes(
vpr_device_ctx.grid, vpr_device_ctx.arch->through_channel, clk_ntwk);
vpr_device_ctx.rr_graph_builder.reserve_nodes(num_clock_nodes +
orig_num_nodes);
/* TODO: Add clock nodes */
@ -111,10 +115,11 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
/* TODO: Sanity checks */
/* Report number of added clock nodes and edges */
VTR_LOGV(
verbose,
"Appended %lu clock nodes (+%.2f%) and %lu clock edges to routing resource graph.\n",
num_clock_nodes, (float)(num_clock_nodes / orig_num_nodes), num_clock_edges);
VTR_LOGV(verbose,
"Appended %lu clock nodes (+%.2f%) and %lu clock edges to routing "
"resource graph.\n",
num_clock_nodes, (float)(num_clock_nodes / orig_num_nodes),
num_clock_edges);
return CMD_EXEC_SUCCESS;
}