Implement some of the final changes

docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst

@@ -1,20 +1,20 @@
-Integrating Custom Verilog Modules with user_defined_templates.v
+Integrating Custom Verilog Modules with user_defined_template.v
 ================================================================
 Introduction and Setup
 ~~~~~~~~~~~~~~~~~~~~~~
 **In this tutorial, we will**
-   - Provide motivation for generating the user_defined_templates.v verilog file
+   - Provide motivation for generating the user_defined_template.v verilog file
-   - Go through a generated user_defined_templates.v file to demonstrate how to use it
+   - Go through a generated user_defined_template.v file to demonstrate how to use it
-Through this example, we will motivate and show how to use the ``user_defined_templates.v`` file.
+Through this example, we will motivate and show how to use the ``user_defined_template.v`` file.
 
 For this examaple, we are using a modified version of the hard adder task that comes with OpenFPGA.
 To follow along, go to the root directory of OpenFPGA and enter: 
 
-.. code-block:: XML
+.. code-block:: bash
 
    vi openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml 
 
-Go to line 187 and replace it with:
+Go to **LINE187** and replace it with:
 
 .. code-block:: XML
 
@@ -24,13 +24,13 @@ Motivation
 ~~~~~~~~~~
 From the OpenFPGA root directory run the command
 
-.. code-block:: XML
+.. code-block:: bash
 
    python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
 
 Running this command should fail and produce these errors:
 
-.. code-block:: XML
+.. code-block:: bash
    
    ERROR - iverilog_verification run failed with returncode 21
    ERROR - command iverilog -o compiled_and2 ./SRC/and2_include_netlists.v -s and2_top_formal_verification_random_tb
@@ -60,37 +60,38 @@ Running this command should fail and produce these errors:
    ERROR - Exiting . . . . . .
 This error log can be found by running the following command from the root directory:
 
-.. code-block:: XML
+.. code-block:: bash
 
    cat openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/00_and2_MIN_ROUTE_CHAN_WIDTH_out.log
 
-This command failed during the verification step because the path to the module definition for ADDF is missing. In our architecture file, user-defined verilog modules are those ``<circuit_model>`` with the key term `verilog_netlist`. The ``user_defined_templates.v`` file provides a module template for incorporating Hard IPs with no external library into the architecture. 
+This command failed during the verification step because the path to the module definition for **ADDF** is missing. In our architecture file, user-defined verilog modules are those ``<circuit_model>`` with the key term `verilog_netlist`. The ``user_defined_template.v`` file provides a module template for incorporating Hard IPs with no external library into the architecture. 
 
 Fixing the Error
 ~~~~~~~~~~~~~~~~
-This error can be resolved by replacing the line 187 of ``k6_frac_N10_adder_chain_40nm_openfpga.xml`` with the following:
+This error can be resolved by replacing the **LINE187** of ``k6_frac_N10_adder_chain_40nm_openfpga.xml`` with the following:
 
 .. code-block:: XML
 
    <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/adder.sp"     verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/adder.v">
 
-The above line provides a path to generate the ``user_defined_templates.v`` file. 
+The above line provides a path to generate the ``user_defined_template.v`` file. 
 Now we can return to the root directory and run this command again:
 
-.. code-block:: XML
+.. code-block:: bash
 
    python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
 
-Fixing the Error with user_defined_templates.v
+Fixing the Error with user_defined_template.v
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-The `user_defined_templates.v`_ file can be found starting from the root directory and entering:
+The `user_defined_template.v`_ file can be found starting from the root directory and entering:
 
-.. code-block:: XML
+.. code-block:: bash
 
-   vi openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/user_defined_templates.v
+   vi openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/user_defined_template.v
 
-This file contains user-defined verilog modules that are found in the openfpga_cell_library with ports declaration (compatible with other netlists that are auto-generated by OpenFPGA) but without functionality. The file is used as a reference for engineers to check what is the port sequence required by top-level verilog netlists. This file can be included in simulation only if there are modifications to the file.
+.. note:: This file contains user-defined verilog modules that are found in the openfpga_cell_library with ports declaration (compatible with other netlists that are auto-generated by OpenFPGA) but without functionality. The file is used as a reference for engineers to check what is the port sequence required by top-level verilog netlists. This file can be included in simulation only if there are modifications to the file.
-To implement our own ADDF module, we need to remove all other module definitions (they are already defined elsewhere and will cause an error if left in). Replace the ``user_defined_templates.v`` file with the following:
+
+To implement our own **ADDF** module, we need to remove all other module definitions (they are already defined elsewhere and will cause an error if left in). Replace the ``user_defined_template.v`` file with the following:
 
 .. code-block:: Verilog
 
@@ -141,27 +142,27 @@ To implement our own ADDF module, we need to remove all other module definitions
    endmodule
    // ----- END Verilog module for ADDF -----
 
-We can now link this ``user_defined_templates.v`` into ``k6_frac_N10_adder_chain_40nm_openfpga.xml``.
+We can now link this ``user_defined_template.v`` into ``k6_frac_N10_adder_chain_40nm_openfpga.xml``.
 
-.. note:: Be sure to select the run where you modified the ``user_defined_templates.v``!
+.. note:: Be sure to select the run where you modified the ``user_defined_template.v``!
 
 From the OpenFPGA root directory, run:
 
-.. code-block:: XML
+.. code-block:: bash
 
    vi openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
 
-At line 187 in verilog_netlist, put in:
+At **LINE187** in verilog_netlist, put in:
 
 .. code-block:: XML
 
-   ${OPENFPGA_PATH}/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/**YOUR_RUN_NUMBER**/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/user_defined_templates.v
+   ${OPENFPGA_PATH}/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/**YOUR_RUN_NUMBER**/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/user_defined_template.v
 
 Finally, rerun this command from the OpenFPGA root directory to ensure it is working:
 
-.. code-block:: XML
+.. code-block:: bash
 
    python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
 
 
-.. _user_defined_templates.v: https://openfpga--274.org.readthedocs.build/en/274/manual/fpga_verilog/fabric_netlist/#cmdoption-arg-user_defined_templates.v
+.. _user_defined_template.v: https://openfpga--274.org.readthedocs.build/en/274/manual/fpga_verilog/fabric_netlist/#cmdoption-arg-user_defined_templates.v