From 8edfc79f53b76751e0dc25373c5767794fe2c121 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 20:11:21 -0600 Subject: [PATCH] [Architecture] Rename AIB cell --- openfpga_flow/VerilogNetlists/aib.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/aib.v b/openfpga_flow/VerilogNetlists/aib.v index 2ebfd5cea..86ea4f671 100644 --- a/openfpga_flow/VerilogNetlists/aib.v +++ b/openfpga_flow/VerilogNetlists/aib.v @@ -5,12 +5,12 @@ // Coder : Xifan Tang //----------------------------------------------------- -module aib ( - input tx_clk, - input rx_clk, - inout[0:79] pad, - input[0:79] tx_data, - output[0:79] rx_data); +module AIB ( + input TXCLK, + input RXCLK, + inout[0:79] PAD, + input[0:79] TXDATA, + output[0:79] RXDATA); // May add the logic function of a real AIB // Refer to the offical AIB github