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bug fixed in flatten memory organization. Passed verification

This commit is contained in:
tangxifan 2020-05-30 12:16:41 -06:00
parent 5f6a790eff
commit 8ec8ac4118
4 changed files with 45 additions and 19 deletions
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4
openfpga/src/fabric/build_memory_modules.cpp
View File

@ -61,7 +61,7 @@ void add_module_input_nets_to_mem_modules(ModuleManager& module_manager,
module_manager.add_module_net_source(mem_module, net, mem_module, 0, src_port_id, src_pin_id);
}
for (size_t pin_id = 0; pin_id < module_manager.module_port(mem_module, sink_port_id).pins().size(); ++pin_id) {
for (size_t pin_id = 0; pin_id < module_manager.module_port(child_module, sink_port_id).pins().size(); ++pin_id) {
/* Sink node of the input net is the input of sram module */
size_t sink_pin_id = module_manager.module_port(child_module, sink_port_id).pins()[pin_id];
module_manager.add_module_net_sink(mem_module, net, child_module, child_instance, sink_port_id, sink_pin_id);
@ -328,7 +328,7 @@ void build_memory_flatten_module(ModuleManager& module_manager,
BasicPort bl_port(std::string(MEMORY_BL_PORT_NAME), num_mems);
ModulePortId mem_bl_port = module_manager.add_port(mem_module, bl_port, ModuleManager::MODULE_INPUT_PORT);
BasicPort wl_port(std::string(MEMORY_BL_PORT_NAME), num_mems);
BasicPort wl_port(std::string(MEMORY_WL_PORT_NAME), num_mems);
ModulePortId mem_wl_port = module_manager.add_port(mem_module, wl_port, ModuleManager::MODULE_INPUT_PORT);
/* Add each output port: port width should match the number of memories */

21
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -913,27 +913,27 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp,
print_verilog_comment(fp, "----- Configuration chain default input -----");
fp << "\t\t";
fp << generate_verilog_port_constant_values(bl_port, initial_bl_values);
fp << ";";
fp << ";" << std::endl;
fp << "\t\t";
fp << generate_verilog_port_constant_values(wl_port, initial_wl_values);
fp << ";";
fp << ";" << std::endl;
fp << std::endl;
fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
fp << "\t\t\t";
fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ") begin" << std::endl;
/* Enable all the WLs */
std::vector<size_t> enabled_wl_values(wl_port.get_width(), 1);
fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_port);
fp << " = ";
fp << "\t\t\t";
fp << generate_verilog_port_constant_values(wl_port, enabled_wl_values);
fp << ";" << std::endl;
size_t ibit = 0;
for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
BasicPort cur_bl_port(bl_port);
cur_bl_port.set_width(ibit, ibit);
fp << "\t\t\t";
fp << generate_verilog_port(VERILOG_PORT_CONKT, cur_bl_port);
fp << " = ";
fp << "1'b" << (size_t)bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id));
@ -942,14 +942,14 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp,
ibit++;
}
fp << "\tend" << std::endl;
fp << "\t\tend" << std::endl;
/* Disable all the WLs */
fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_port);
fp << " = ";
fp << generate_verilog_port_constant_values(wl_port, initial_wl_values);
fp << "\t\t\t";
fp << generate_verilog_port_constant_values(wl_port, initial_wl_values);
fp << ";" << std::endl;
/* Raise the flag of configuration done when bitstream loading is complete */
fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
@ -966,7 +966,6 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp,
print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----");
}
/********************************************************************
* Print stimulus for a FPGA fabric with a configuration chain protocol
* where configuration bits are programming in serial (one by one)

36
openfpga/src/fpga_verilog/verilog_writer_utils.cpp
View File

@ -644,12 +644,38 @@ std::string generate_verilog_local_wire(const BasicPort& output_port,
/********************************************************************
* Generate a string for a constant value in Verilog format:
* <#.of bits>'b<binary numbers>
*
* Optimization: short_constant
* When this switch is turned on, we will generate short version
* for all-zero/all-one vectors
* {<length>{1'b<zero/one>}}
*******************************************************************/
std::string generate_verilog_constant_values(const std::vector<size_t>& const_values) {
std::string str = std::to_string(const_values.size());
str += "'b";
for (const auto& val : const_values) {
str += std::to_string(val);
std::string generate_verilog_constant_values(const std::vector<size_t>& const_values,
const bool& short_constant) {
VTR_ASSERT(!const_values.empty());
bool same_values = true;
size_t first_val = const_values.back();
if (true == short_constant) {
for (const auto& val : const_values) {
if (first_val != val) {
same_values = false;
break;
}
}
}
std::string str;
if ( (true == short_constant)
&& (true == same_values) ) {
str = "{" + std::to_string(const_values.size()) + "{1'b" + std::to_string(first_val) + "}}";
} else {
str = std::to_string(const_values.size());
str += "'b";
for (const auto& val : const_values) {
str += std::to_string(val);
}
}
return str;
}

3
openfpga/src/fpga_verilog/verilog_writer_utils.h
View File

@ -96,7 +96,8 @@ BasicPort generate_verilog_bus_port(const std::vector<BasicPort>& input_ports,
std::string generate_verilog_local_wire(const BasicPort& output_port,
const std::vector<BasicPort>& input_ports);
std::string generate_verilog_constant_values(const std::vector<size_t>& const_values);
std::string generate_verilog_constant_values(const std::vector<size_t>& const_values,
const bool& short_constant = false);
std::string generate_verilog_port_constant_values(const BasicPort& output_port,
const std::vector<size_t>& const_values);