bug fixed in flatten memory organization. Passed verification
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5f6a790eff
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@ -61,7 +61,7 @@ void add_module_input_nets_to_mem_modules(ModuleManager& module_manager,
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module_manager.add_module_net_source(mem_module, net, mem_module, 0, src_port_id, src_pin_id);
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}
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for (size_t pin_id = 0; pin_id < module_manager.module_port(mem_module, sink_port_id).pins().size(); ++pin_id) {
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for (size_t pin_id = 0; pin_id < module_manager.module_port(child_module, sink_port_id).pins().size(); ++pin_id) {
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/* Sink node of the input net is the input of sram module */
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size_t sink_pin_id = module_manager.module_port(child_module, sink_port_id).pins()[pin_id];
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module_manager.add_module_net_sink(mem_module, net, child_module, child_instance, sink_port_id, sink_pin_id);
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@ -328,7 +328,7 @@ void build_memory_flatten_module(ModuleManager& module_manager,
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BasicPort bl_port(std::string(MEMORY_BL_PORT_NAME), num_mems);
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ModulePortId mem_bl_port = module_manager.add_port(mem_module, bl_port, ModuleManager::MODULE_INPUT_PORT);
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BasicPort wl_port(std::string(MEMORY_BL_PORT_NAME), num_mems);
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BasicPort wl_port(std::string(MEMORY_WL_PORT_NAME), num_mems);
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ModulePortId mem_wl_port = module_manager.add_port(mem_module, wl_port, ModuleManager::MODULE_INPUT_PORT);
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/* Add each output port: port width should match the number of memories */
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@ -913,27 +913,27 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp,
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print_verilog_comment(fp, "----- Configuration chain default input -----");
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fp << "\t\t";
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fp << generate_verilog_port_constant_values(bl_port, initial_bl_values);
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fp << ";";
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fp << ";" << std::endl;
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fp << "\t\t";
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fp << generate_verilog_port_constant_values(wl_port, initial_wl_values);
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fp << ";";
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fp << ";" << std::endl;
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fp << std::endl;
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fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
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fp << "\t\t\t";
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fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ") begin" << std::endl;
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/* Enable all the WLs */
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std::vector<size_t> enabled_wl_values(wl_port.get_width(), 1);
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fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_port);
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fp << " = ";
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fp << "\t\t\t";
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fp << generate_verilog_port_constant_values(wl_port, enabled_wl_values);
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fp << ";" << std::endl;
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size_t ibit = 0;
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for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
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BasicPort cur_bl_port(bl_port);
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cur_bl_port.set_width(ibit, ibit);
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fp << "\t\t\t";
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fp << generate_verilog_port(VERILOG_PORT_CONKT, cur_bl_port);
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fp << " = ";
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fp << "1'b" << (size_t)bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id));
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@ -942,14 +942,14 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp,
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ibit++;
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}
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fp << "\tend" << std::endl;
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fp << "\t\tend" << std::endl;
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/* Disable all the WLs */
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fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
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fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_port);
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fp << " = ";
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fp << generate_verilog_port_constant_values(wl_port, initial_wl_values);
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fp << "\t\t\t";
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fp << generate_verilog_port_constant_values(wl_port, initial_wl_values);
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fp << ";" << std::endl;
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/* Raise the flag of configuration done when bitstream loading is complete */
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fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
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@ -966,7 +966,6 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp,
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print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----");
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}
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/********************************************************************
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* Print stimulus for a FPGA fabric with a configuration chain protocol
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* where configuration bits are programming in serial (one by one)
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@ -644,13 +644,39 @@ std::string generate_verilog_local_wire(const BasicPort& output_port,
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/********************************************************************
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* Generate a string for a constant value in Verilog format:
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* <#.of bits>'b<binary numbers>
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*
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* Optimization: short_constant
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* When this switch is turned on, we will generate short version
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* for all-zero/all-one vectors
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* {<length>{1'b<zero/one>}}
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*******************************************************************/
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std::string generate_verilog_constant_values(const std::vector<size_t>& const_values) {
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std::string str = std::to_string(const_values.size());
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std::string generate_verilog_constant_values(const std::vector<size_t>& const_values,
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const bool& short_constant) {
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VTR_ASSERT(!const_values.empty());
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bool same_values = true;
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size_t first_val = const_values.back();
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if (true == short_constant) {
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for (const auto& val : const_values) {
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if (first_val != val) {
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same_values = false;
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break;
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}
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}
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}
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std::string str;
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if ( (true == short_constant)
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&& (true == same_values) ) {
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str = "{" + std::to_string(const_values.size()) + "{1'b" + std::to_string(first_val) + "}}";
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} else {
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str = std::to_string(const_values.size());
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str += "'b";
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for (const auto& val : const_values) {
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str += std::to_string(val);
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}
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}
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return str;
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}
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@ -96,7 +96,8 @@ BasicPort generate_verilog_bus_port(const std::vector<BasicPort>& input_ports,
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std::string generate_verilog_local_wire(const BasicPort& output_port,
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const std::vector<BasicPort>& input_ports);
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std::string generate_verilog_constant_values(const std::vector<size_t>& const_values);
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std::string generate_verilog_constant_values(const std::vector<size_t>& const_values,
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const bool& short_constant = false);
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std::string generate_verilog_port_constant_values(const BasicPort& output_port,
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const std::vector<size_t>& const_values);
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