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Merge with heterogeneous for unfracturable LUT bug fix

This commit is contained in:
AurelienUoU 2019-08-14 10:10:27 -06:00
parent df873903f8
commit 8e38aa6019
2 changed files with 20 additions and 20 deletions
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38
fpga_flow/benchmarks/List/mcnc_benchmark.txt
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@ -1,21 +1,21 @@
# Circuit Names, fixed routing channel width, # Circuit Names, fixed routing channel width,
#alu4/*.v, 300 alu4/*.v, 300
#apex2/*.v, 300 apex2/*.v, 300
#apex4/*.v, 300 apex4/*.v, 300
#bigkey/*.v, 300 bigkey/*.v, 300
#clma/*.v, 300 clma/*.v, 300
#des/*.v, 300 des/*.v, 300
#diffeq/*.v, 300 diffeq/*.v, 300
#dsip/*.v, 300 dsip/*.v, 300
#elliptic/*.v, 300 elliptic/*.v, 300
#ex1010/*.v, 300 ex1010/*.v, 300
#ex5p/*.v, 300 ex5p/*.v, 300
#frisc/*.v, 300 frisc/*.v, 300
#misex3/*.v, 300 misex3/*.v, 300
#pdc/*.v, 300 pdc/*.v, 300
s298/*.v, 30 s298/*.v, 30
#s38417/*.v, 300 s38417/*.v, 300
#s38584/*.v, 300 s38584/*.v, 300
#seq/*.v, 300 seq/*.v, 300
#spla/*.v, 300 spla/*.v, 300
#tseng/*.v, 300 tseng/*.v, 300

2
vpr7_x2p/vpr/regression_verilog.sh
View File

@ -10,7 +10,7 @@ verilog_output_dirpath="$PWD"
tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml" tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml"
# VPR critical inputs # VPR critical inputs
template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml" template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml"
arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC_DPRAM.xml" arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml"
blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif" blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif"
act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act " act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act "
verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v" verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v"