From 8e381f05815a9917ded35b172398a2f16310ec35 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 19:57:15 -0700
Subject: [PATCH] add wire module builder

---
 openfpga/src/fabric/build_device_module.cpp |  4 +-
 openfpga/src/fabric/build_wire_modules.cpp  | 73 +++++++++++++++++++++
 openfpga/src/fabric/build_wire_modules.h    | 22 +++++++
 3 files changed, 97 insertions(+), 2 deletions(-)
 create mode 100644 openfpga/src/fabric/build_wire_modules.cpp
 create mode 100644 openfpga/src/fabric/build_wire_modules.h

diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp
index 5e8b090f2..a7c82f351 100644
--- a/openfpga/src/fabric/build_device_module.cpp
+++ b/openfpga/src/fabric/build_device_module.cpp
@@ -12,7 +12,7 @@
 #include "build_decoder_modules.h"
 #include "build_mux_modules.h"
 #include "build_lut_modules.h"
-//#include "build_wire_modules.h"
+#include "build_wire_modules.h"
 //#include "build_memory_modules.h"
 //#include "build_grid_modules.h"
 //#include "build_routing_modules.h"
@@ -59,7 +59,7 @@ ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
   build_lut_modules(module_manager, openfpga_ctx.arch().circuit_lib);
 
   /* Build wire modules */
-  //build_wire_modules(module_manager, arch.spice->circuit_lib);
+  build_wire_modules(module_manager, openfpga_ctx.arch().circuit_lib);
 
   /* Build memory modules */
   //build_memory_modules(module_manager, mux_lib, arch.spice->circuit_lib,
diff --git a/openfpga/src/fabric/build_wire_modules.cpp b/openfpga/src/fabric/build_wire_modules.cpp
new file mode 100644
index 000000000..da3b03e23
--- /dev/null
+++ b/openfpga/src/fabric/build_wire_modules.cpp
@@ -0,0 +1,73 @@
+/***********************************************
+ * This file includes functions to generate
+ * Verilog submodules for wires.
+ **********************************************/
+#include <string>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+/* Device-level header files */
+#include "module_manager.h"
+#include "module_manager_utils.h"
+
+#include "openfpga_naming.h"
+
+#include "build_wire_modules.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print a Verilog module of a regular wire segment
+ * Regular wire, which is 1-input and 1-output
+ * This type of wires are used in the local routing architecture
+ *              +------+
+ *    input --->| wire |---> output
+ *              +------+
+ *
+ *******************************************************************/
+static 
+void build_wire_module(ModuleManager& module_manager, 
+                       const CircuitLibrary& circuit_lib,
+                       const CircuitModelId& wire_model) {
+  /* Find the input port, output port*/
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(wire_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(wire_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(wire_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
+
+  /* Makre sure the port size is what we want */
+  VTR_ASSERT (1 == input_ports.size());
+  VTR_ASSERT (1 == output_ports.size());
+  VTR_ASSERT (1 == circuit_lib.port_size(input_ports[0]));
+  VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0]));
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  add_circuit_model_to_module_manager(module_manager, circuit_lib, wire_model); 
+}
+
+/********************************************************************
+ * This function will only create wire modules with a number of 
+ * ports that are defined by users.
+ * It will NOT insert any internal logic, which should be handled 
+ * by Verilog/SPICE writers
+ *******************************************************************/
+void build_wire_modules(ModuleManager& module_manager,
+                        const CircuitLibrary& circuit_lib) {
+  vtr::ScopedStartFinishTimer timer("Build wire modules");
+
+  /* Print Verilog models for regular wires*/
+  for (const auto& wire_model : circuit_lib.models_by_type(CIRCUIT_MODEL_WIRE)) { 
+    /* Bypass user-defined circuit models */
+    if ( (!circuit_lib.model_circuit_netlist(wire_model).empty()) 
+      && (!circuit_lib.model_verilog_netlist(wire_model).empty()) ) {
+      continue;
+    }
+    build_wire_module(module_manager, circuit_lib, wire_model);
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_wire_modules.h b/openfpga/src/fabric/build_wire_modules.h
new file mode 100644
index 000000000..845f5f532
--- /dev/null
+++ b/openfpga/src/fabric/build_wire_modules.h
@@ -0,0 +1,22 @@
+#ifndef BUILD_WIRE_MODULES_H
+#define BUILD_WIRE_MODULES_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "circuit_library.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void build_wire_modules(ModuleManager& module_manager,
+                        const CircuitLibrary& circuit_lib);
+
+} /* end namespace openfpga */
+
+#endif