From 8e36ed1ab65fa111fca82ce1d35f7a8f371b105f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Feb 2021 15:01:15 -0700 Subject: [PATCH] [Test] Update task configuration to use and2 eblif --- .../tasks/fpga_verilog/adder/soft_adder/config/task.conf | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf index 93f0c2d6a..fcf40502f 100644 --- a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf @@ -9,7 +9,7 @@ [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true +power_analysis = false spice_output=false verilog_output=true timeout_each_job = 1*60 @@ -26,12 +26,12 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]